Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate cache and TLB
3. set translation table entries , point ttbr register to translation table.
4.enable cache, branch predictor
5. enable MMU.
Queries
1. I need help to understand how the translation table entries are defined.. If i choose 1MB section option then
how can i make entry for External flash memory which is of 16MB.
Here we have different memory regions, internal Ram(1MB), internal flash(4MB), External flash(16MB) and so on..
How can i define translation table entries for the above mentioned memory regions.
2. Translation tables are stored in main memory, here main memory is RAM ???
3 How can we check all the above steps working or not in trace32 ??
by executing the command cache.view i am able to see the cache content but i am unable to understand it.
Thanks in Advance.
ZbinAhmed