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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3627 Questions
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  • Not Answered

    Unable to determine offending instruction: usage fault illegal unaligned load or store cortex m7 keil mdk pro 0

    • Cortex-M7
    • 3 (HardFault)
    • 6 (UsageFault)
    7526 views
    2 replies
    Latest over 6 years ago
    by mzu2006
  • Answered

    When the generic timer starts to tick? 0

    21090 views
    2 replies
    Latest over 6 years ago
    by rzsz
  • Answered

    [DS-5] Is it possible to set a watchpoint on a spec reg? +1

    • DS-5 Debugger
    19670 views
    1 reply
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Arm Really Should Standardize An SMC Interface For Hardware Random Number Generators 0

    • Arm Trusted Firmware
    • SMCCC
    • Server Base System Architecture (SBSA)
    21500 views
    2 replies
    Latest over 6 years ago
    by myfreeweb
  • Answered

    Can i change SP at run time in CM33? 0

    • Arm Development Studio
    • Cortex-M33
    • Armv8-M
    11859 views
    12 replies
    Latest over 6 years ago
    by Deepak
  • Not Answered

    Running an app on big and LITTLE cores simultaneously? 0

    17762 views
    0 replies
    Started over 6 years ago
    by nsn
  • Not Answered

    Just a processor? 0

    3998 views
    4 replies
    Latest over 6 years ago
    by Marcelo Jayme Arm Employee Badge
  • Answered

    Memory Protection Unit - Complexity in usage +1

    9653 views
    7 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Monitor Mode Debug 0

    7795 views
    7 replies
    Latest over 6 years ago
    by Andy Neil
  • Answered

    32-bit encoding hex values for Arm instructions 0

    6520 views
    3 replies
    Latest over 6 years ago
    by BQL
  • Answered

    Cycle count for a subroutine on Cortex M33 0

    8495 views
    2 replies
    Latest over 6 years ago
    by Ed Player Arm Employee Badge
  • Answered

    TrustZone in CortexR +1

    • Cortex-R
    • virtualization
    • TrustZone
    9872 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Where to find hard core Arm books, courses, tutorials 0

    • Arm7tdmi
    10528 views
    6 replies
    Latest over 6 years ago
    by drake00
  • Suggested Answer

    arm1176jzf-s fiq context switch 0

    19706 views
    1 reply
    Latest over 6 years ago
    by Peter Rielly Arm Employee Badge
  • Not Answered

    A72 not handling IRQ properly 0

    • Cortex-A72
    • Interrupt Handling
    18687 views
    0 replies
    Started over 6 years ago
    by MNB
  • Answered

    Debug Unit Cortex - R 0

    6543 views
    3 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Cortex-M: Does the event register only get set when an IRQ changes from not pending to pending? 0

    • Interrupt Handling
    • event
    • Cortex-M4
    7733 views
    3 replies
    Latest over 6 years ago
    by m.wagner
  • Answered

    Is CPSR.F settable through debug port? (e.g. JTAG) +1

    • Cortex-R5
    • CPSR
    • Debugging
    6166 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Instruction Fault Generation +1

    5528 views
    2 replies
    Latest over 6 years ago
    by techguyz
  • Answered

    Disable data prefetching in a Cortex-A53 running Android +1

    • Cortex-A53
    • EL1
    • L1
    • L2
    27088 views
    6 replies
    Latest over 6 years ago
    by DNovo
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