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Cortex A53 : Cache policy setting

Hi,

Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor?

I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory as inner sharable and normal write back. With this programming what is the caching policy will be set by the cpu.

Thanks,

Prabhu

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MarekBykowski over 6 years ago +1 verified

For inner caches I suggest a read out, eg. D4.4 VMSAv8-64 translation table format descriptors of ARM ® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. If you look at the page...

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0 42Bastian Schick over 6 years ago in reply to MarekBykowski

Marek, what do you been by CCN. (Acronyms are nice, if easy to find and google, but CCN ?!)
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0 42Bastian Schick over 6 years ago in reply to MarekBykowski

Marek, what do you been by CCN. (Acronyms are nice, if easy to find and google, but CCN ?!)
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0 42Bastian Schick over 6 years ago in reply to 42Bastian Schick

Ah, finally found it: ARM CCN-504 Cache Coherent Network
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0 MarekBykowski over 6 years ago in reply to 42Bastian Schick

Yes Bastian. CCN family includes CoreLink CCN-512, 508, 504 and 502 developer.arm.com/.../corelink-cache-coherent-network-family. I have worked with the SOCs featuring 512 and 504. But taking similarities across the two the others should be very close too.
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