• State Accepted Answer
  • Locked Locked
  • Replies 4 replies
  • Subscribers 348 subscribers
  • Views 8224 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex A53 : Cache policy setting

PrabhuKrishnan

Hi,

Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? 

I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory as inner sharable and normal write back. With this programming what is the caching policy will be set by the cpu. 

Thanks,

Prabhu

Parents
  • +1

    For inner caches I suggest a read out, eg. D4.4 VMSAv8-64 translation table format descriptors of ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. 

    If you look at the page descriptor there is AttrIndx[2:0], bits[4:2]. AttrIndex gives the value of n of the MAIR register which is split to 8 attributes each 8 bits. For instance if Attr<n>[7:4] is 1111 and Attr<n>[3:0] 1111 then you have Normal Memory, Inner Write-back non-transient, Read and Write Allocate.

    For outer caches such L3 in CCN you should read the corresponding manual.

Reply
  • +1

    For inner caches I suggest a read out, eg. D4.4 VMSAv8-64 translation table format descriptors of ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile. 

    If you look at the page descriptor there is AttrIndx[2:0], bits[4:2]. AttrIndex gives the value of n of the MAIR register which is split to 8 attributes each 8 bits. For instance if Attr<n>[7:4] is 1111 and Attr<n>[3:0] 1111 then you have Normal Memory, Inner Write-back non-transient, Read and Write Allocate.

    For outer caches such L3 in CCN you should read the corresponding manual.

Children