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When to enable ARM Cortex A8 L1 cache parity detection

Hi,

Our design use Cortex-A8 based AM335x.
We would like to know when to Enable the L1 cache parity(L1PE bit).
Is it before Cache invalidation or after Cache invalidation?
Couldn't find the procedure to enable L1 cache parity in Cortex-A8 manual.

Best Regards

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42Bastian Schick over 7 years ago +1 verified

I'd follow common sense: Disable cache, invalidate, enable parity, enable cache.
42Bastian Schick over 7 years ago in reply to Paddu +1 verified

I'd say it is only essential to do both invalidate and enabling while the cache is turned off. The parity is on the cache contents only AFAIK.

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+1 42Bastian Schick over 7 years ago in reply to Paddu

I'd say it is only essential to do both invalidate and enabling while the cache is turned off. The parity is on the cache contents only AFAIK.
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+1 42Bastian Schick over 7 years ago in reply to Paddu

I'd say it is only essential to do both invalidate and enabling while the cache is turned off. The parity is on the cache contents only AFAIK.
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