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When to enable ARM Cortex A8 L1 cache parity detection

Hi,

Our design use Cortex-A8 based AM335x.
We would like to know when to Enable the L1 cache parity(L1PE bit).
Is it before Cache invalidation or after Cache invalidation?
Couldn't find the procedure to enable L1 cache parity in Cortex-A8 manual.

Best Regards

Top replies

42Bastian Schick over 7 years ago +1 verified

I'd follow common sense: Disable cache, invalidate, enable parity, enable cache.
42Bastian Schick over 7 years ago in reply to Paddu +1 verified

I'd say it is only essential to do both invalidate and enabling while the cache is turned off. The parity is on the cache contents only AFAIK.

Parents

0 Paddu over 7 years ago in reply to 42Bastian Schick

Thank you.

I am sorry for asking the basic question.
In our current application, the parity is enabled
before invalidate as shown below.

1>Disable cache->2.Enable parity->3.Invalidate->4.Enable cache.

will this have any problem.
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0 Paddu over 7 years ago in reply to 42Bastian Schick

Thank you.

I am sorry for asking the basic question.
In our current application, the parity is enabled
before invalidate as shown below.

1>Disable cache->2.Enable parity->3.Invalidate->4.Enable cache.

will this have any problem.
Cancel
Up 0 Down

Cancel

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+1 42Bastian Schick over 7 years ago in reply to Paddu

I'd say it is only essential to do both invalidate and enabling while the cache is turned off. The parity is on the cache contents only AFAIK.
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