Hi,
On 32-bit and 64-bit cortex, can we have flat memory management (physical address == virtual address) to remove the cost of a page walk, while not losing on performance (keeping instruction and data caches active)?
Or at least, during the page fault interrupt, may we designate the address to fetch the page from (simple calculation + 1 memory access instead of multiple memory access), avoiding the page table walk?
I am trying to find a way to cancel the need for that slow operation.
Thanks
PowerPC CPUs allow to write TLB entries directly. A nice feature.