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Flat memory model

MarkL

Hi,

On 32-bit and 64-bit cortex, can we have flat memory management (physical address == virtual address) to remove the cost of a page walk, while not losing on performance (keeping instruction and data caches active)?

Or at least, during the page fault interrupt, may we designate the address to fetch the page from (simple calculation + 1 memory access instead of multiple memory access), avoiding the page table walk?

I am trying to find a way to cancel the need for that slow operation.

Thanks

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  • +1

    Interesting question.

    So, with the MMU disabled you get the flat mapping for free.  The downside is that data memory becomes non-cacheable.  (I guess on the cores with virtualization you could use the default cachability upgrade (HCR_EL2.DC) but without stage 2 translation'real' device memory might become unsafe.)

    The only real option is to enable the MMU and flat-map the memory using appropriate memory types.  You can never totally avoid table walks but if you can structure your tables so that mapping are in the TLBs you can reduce them.  This can be done by mapping memory using larger page sizes, which is also easier to do for flat mapped memory layouts.

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  • +1

    Interesting question.

    So, with the MMU disabled you get the flat mapping for free.  The downside is that data memory becomes non-cacheable.  (I guess on the cores with virtualization you could use the default cachability upgrade (HCR_EL2.DC) but without stage 2 translation'real' device memory might become unsafe.)

    The only real option is to enable the MMU and flat-map the memory using appropriate memory types.  You can never totally avoid table walks but if you can structure your tables so that mapping are in the TLBs you can reduce them.  This can be done by mapping memory using larger page sizes, which is also easier to do for flat mapped memory layouts.

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