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Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Hello Preet Kaur Walia,
I think if (addr_done & rvalid & rready_new)would be wrong.The count start trigger should be the rising edge of "rvalid & rready".Therefore, the if statement should be replaced withif (addr_done & ~delayed_rvalid_rready & (rvalid_pre_mask & rready_pre_mask)).Here,awalways@(posedge clk) delayed_rvalid_rready <= rvalid_pre_mask & rready_pre_mask;
Best regards,Yasuhiko Koumoto.
Sir
the statement
if (addr_done & ~delayed_rvalid_rready & (rvalid_pre_mask & rready_pre_mask))
How will this statement be responsible for checking the rising edge of the ready and valid signals.
Instead can i do this:
always@(posedge clk)
dealyed_rvalid_rready<=rvalid & rready;
always@(posedge clk or posedge count_in)
begin
case(state)
0: begin
if (count_in)
addr_done<=1;
state <= 1;
end
else
addr_done<=0;
state<=0;
1: begin
if (rvalid_i & rready & rlast)
state <= 0;
endcase
always@(posedge clk or dealyed_rvalid_rready)
case(state_delay)
if ( addr_done & dealyed_rvalid_rready)
state_delay<=1;
mask <=1;//provide delay as required by masking
state_delay<=0;
mask <=0;//stop the masking
Regards
Preet Kaur Walia
Hi Preet Kaur Walia,
I think your HDL description would generate the latch instead of the flip-flop. Is it OK?
Honestry speaking, I cannot understnd your HDL.
Is it working well?
Best regards,
Yasuhiko Koumoto.
No sir
Even after using the code below I am able to read the value written to previous address .
For example if i try to read 0x11111111 of my memory I read the value written to 0x11111110.I am using AXI bus to read.
assign count_in = arvalid and arready;
always@(posedge clk) //as suggested by you
delayed_rvalid_rready<=rvalid_i & rready;
always@(posedge clk )
if ( addr_done & ~dealyed_rvalid_rready & (rvalid_i & rready))
mask <=0;
1:begin
mask <=1;///so on for 15 cycle
state_delay<=2;
2: begin
mask <=1;
state_delay<=3;
15:
rdata_delayed<=rd_data ;
mask<=0;
first of all,
"For example if i try to read 0x11111111 of my memory I read the value written to 0x11111110.I am using AXI bus to read. "
would be impossible.
There is possibility to read the data before being written at 0x11111111.
This time, there is no consideration of such the read-after-write problem.
I think that there seems be some misunderstandings.
My proposal is to insert 15 cycle delay one time for one read or write transaction. It seems that you want to insert 15 cycle delay for each data cycle.
Please show us your timing diagram instead of HDL descriptions.
By the way, what is the number of outstandings by your master?
I only consider the number of outstandings is one.
Yes for each data cycle I want to add the delay for read and write transaction. For example in burst mode if I read 64 data words from memory. I want each of the read to be delayed by 15 clock cycles. As of the timing diagrams is considered I was following the timing provided by you to achieve the situation for read and write.
For write, the circuit diagram provided by you works for delaying each write(each datapath write and not one complete write transaction containing several data words written but delay to each dataword) by 15 clock cycles but the same is not happening for read(I am following your timing diagram.)
As I have understandood the outstandings by master(heer Mmeory controller block) are the number of transactions to and from the AXI bus can be any number. But maximum number can be 64 data words can be written in single burst. Each dataword width is 64 bits. First of all I want to know the timing diagram you have provided for read will not delay each read dataword? As of now I am assuming my HDL is wrong.
Preet Kaur
As you can see from timing diagram. I am trying to delay my read transaction(every data word in one read transaction) .As rvald and rready posedge arrives I began to mask the rvalid and rready for 15 cycles. For example in diagram below for burst read containing 3 dataword reads I mask the signals thrice and finsh off when rlast arrives. Kindly let me know if this is the correct way to delay each read dataword. My prime motive is to modify each dataword being written to memory.(in the dealy I am providing).
thank you for the confirmation.My previous idea is wrong because a master will accept the first data response without delay.I think the desired timing would be as following.
To realize the timing I would like to the Verilog descriptions like below.
always@(posedge CLK) begin if(~ARESETN) ADDR_DONE <= 0; else if(ARVALID&masked_ARREADY) ADDR_DONE <= 1; else if(RLAST&RVALID&RREADY) ADDR_DONE <= 0; end akways@(posedge CLK) begin if(~ARESETN) FIRST_DATA_MASK <= 0; else if(ARVALID&masked_ARREADY) FIRST_DATA_MASK <= 1; else if(ADDR_DONE&RVALID&RREADY) FIRST_DATA_MASK <= 0; end akways@(posedge CLK) begin if(~ARESETN) counter <= 4'h0; else if(ADDR_DONE&masked_RVALID&masked_RREADY) counter <= 4'hf; else if(counter!=4'h0) coubter <= counter -1 ; end assign mask_pre = (couner != 4'h0); assign RVALID_mask = FIRST_DATA_MASK | mask_pre; assign RREADY_mask = mask_pre; assign masked_RVALID = RVALID & ~RVALID_mask; // RVALID for master assign masked_RREADY = READY & ~RREADY_mask; // RREADY for slave assign masked_ARREADY = ~ADDR_DONE & ARREADY; // this make outstanding 1
HTH,Yasuhiko Koumoto.
hankyou sir .
I have a few doubts
Firstly,the write circuit you sent to me..will be applicable for delaying each dataword in a write transaction(same situation as read).
Also I am not able to understand the cpncepr of arready.
from what I have understood
assign masked_ARREADY = ~ADDR_DONE & ARREADY; // this make outstanding 1
This masked_arready will be used by used to mask arready or just in the always block you have described in your code?
I am not able to understand this statement. further I have understood the working.
regards
No, it were not. The write logics insert 15 cycle delay one time.However, my new logics which were shown by HDL in the read case will be applicable to the write channel. I think by replacing 'R' for 'W', it will be OK.
This masked_arready will be used by used to mask arready or just in the always block you have described in your code? I am not able to understand this statement.
The aim of the code is to limit the number of read outstandings to one.If the master would issue more than one read addresses before responding the first data, the basic assumption of my logics would be destroyed.
As you can see from the diagram I have taken from the manual of AMBAaxi it states that overlapping read bursts can occur(second address can be sent) without the first data being read back. I have thought of an alternative to this option:
shall i stop the handshaking
axhandshake=arvalid & arready;
instaed
axhandshake=arvalid & mask_arready;
I shall mask arready such that handshaking is not possible.
Also by making outstanding one you mean that the master cannot send second address before first data from first read transaction is read back?
Yes, you shall.
Also by making outstanding one you mean that the master cannot send second address before first data from first
read transaction is read back?
Yes, it does.
I am working on the read and write as per your suggestions.
The read is working fine but write is not.
As you mentioned the write will work similarly but it does not.
If I do a single write it is getting written on memory without delay(I am assuming the first data mask is not working for it)
Burst is not working.
in the write case, you should swap the meaning of data READY and VALID.That is, RREADY to WVALID and RVALID to WREADY conversions will be needed.
always@(posedge CLK) begin if(~ARESETN) WADDR_DONE <= 0; else if(AWVALID&masked_AWREADY) WADDR_DONE <= 1; else if(BVALID&BREADY) WADDR_DONE <= 0; end always@(posedge CLK) begin if(~ARESETN) FIRST_WDATA_MASK <= 0; else if(AWVALID&masked_AWREADY) FIRST_WDATA_MASK <= 1; else if(WADDR_DONE&WVALID&WREADY) FIRST_WDATA_MASK <= 0; end always@(posedge CLK) begin if(~ARESETN) wcounter <= 4'h0; else if(WADDR_DONE&masked_WVALID&masked_WREADY) wcounter <= 4'hf; else if(wcounter!=4'h0) wcoubter <= wcounter -1 ; end assign mask_pre = (wcouner != 4'h0); assign WREADY_mask = FIRST_WDATA_MASK | mask_pre; // CHANGE! assign WVALID_mask = mask_pre; // CHANGE! assign masked_WVALID = WVALID & ~WVALID_mask; // RVALID for master assign masked_WREADY = WREADY & ~WREADY_mask; // RREADY for slave assign masked_AWREADY = ~WADDR_DONE & AWREADY; // this make outstanding 1