This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Halt-on-debug scenario, halt the system counter when halting.

From "I2.2.2 Halt-on-debug", When the CNTCR.HDBG bit is set to 1, and the Halt-on-debug signal is implemented and asserted, the system counter is halted. Otherwise, the system counter ignores the state of this signal.

What are the practical use cases for pausing the system counter through an external debugger? When is it necessary to pause the counter through cross-triggering?

Parents
  • Therefore, when multiple PEs are executing time-sensitive tasks simultaneously, if an external debugger halts one PE, does it need to also halt the system counter to ensure the correctness of timing?

    However, would the other PEs that are still running be unable to obtain the correct time from the system counter because it has been halted?

Reply
  • Therefore, when multiple PEs are executing time-sensitive tasks simultaneously, if an external debugger halts one PE, does it need to also halt the system counter to ensure the correctness of timing?

    However, would the other PEs that are still running be unable to obtain the correct time from the system counter because it has been halted?

Children