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Halt-on-debug scenario, halt the system counter when halting.

From "I2.2.2 Halt-on-debug", When the CNTCR.HDBG bit is set to 1, and the Halt-on-debug signal is implemented and asserted, the system counter is halted. Otherwise, the system counter ignores the state of this signal.

What are the practical use cases for pausing the system counter through an external debugger? When is it necessary to pause the counter through cross-triggering?

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  • Let me understand. In multi-core time-sensitive task scenarios, for the halted core, it is necessary to synchronously halt the global counter to ensure time synchronization.
    However, once the global counter is halted, will it also affect other cores that are running normally?

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  • Let me understand. In multi-core time-sensitive task scenarios, for the halted core, it is necessary to synchronously halt the global counter to ensure time synchronization.
    However, once the global counter is halted, will it also affect other cores that are running normally?

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