Hi experts:
AFAIK, DMB can only ensure relative orders.
But in https://developer.arm.com/documentation/100941/0101/Barriers?lang=en, it says:
It also ensures that any explicit preceding data or unified cache maintenance operations have completed before any subsequent data accesses are executed.
Does DMB can ensure this? I'am a little confused.
Hi digital_kevin,
You are right: this is a simplification. This "Learn the architecture" document explains the barriers in simpler terms than the Architecture Reference Manual.
The DMB does indeed ensures relative order of the instructions' memory effects and cache maintenance operations. It does not ensure completion of those instructions.
I think that in practice, the sentence is mostly true. Ensuring that the effects of some cache maintenance operations such as an invalidate can be observed might be implemented by simply waiting until the cache maintenance instruction has completed.
Hi vstehle,
So, the reason for saying that is due to the implemention of data cache maintenance operations.
For D-cache clean and invalidate operations，We can speak DMB is sufficient(no need using DSB).
I want to learn more about how dmb affects cpu's pipeline.
for examle:
memory access instr1;
dmb;
memory access instr2;
Does it mean the cpu will issue instr1/2 in-order?
Thank you very much.
Maybe. The architecture is guaranteeing that, because of the DMB, you can't see the effect of instr2 without also seeing the effect of instr1. But, the architecture doesn't say anything about how that result is achieved.
One possible approach would be to issue instr1, do the operation, and only then issue instr2. Another approach might to be issue them in whatever order, but record a hazard for the load/store to deal with.