Hi experts:
AFAIK, DMB can only ensure relative orders.
But in https://developer.arm.com/documentation/100941/0101/Barriers?lang=en, it says:
It also ensures that any explicit preceding data or unified cache maintenance operations have completed before any subsequent data accesses are executed.
Does DMB can ensure this? I'am a little confused.
Hi digital_kevin,
You are right: this is a simplification. This "Learn the architecture" document explains the barriers in simpler terms than the Architecture Reference Manual.
The DMB does indeed ensures relative order of the instructions' memory effects and cache maintenance operations. It does not ensure completion of those instructions.
I think that in practice, the sentence is mostly true. Ensuring that the effects of some cache maintenance operations such as an invalidate can be observed might be implemented by simply waiting until the cache maintenance instruction has completed.