If the R5's TCM is configured to reside at location 0x0000 0000 does it hold the exception vector table?
The vector table resides at either 0x0 or 0xffff0000, defined by a pin at reset, and reflected in the V bit of the SCTLR:https://developer.arm.com/documentation/den0042/a/ARM-Processor-modes-and-Registers/Registers/System-Control-Register--SCTLR-
If TCM is at 0x0 and V bit is 0, then yes, you can place the vector table there (and this is a very common scenario). You may have reset behavior that starts from 0xffff0000, then enable and initialize TCM, then clear V bit to enable subsequent exceptions to be handled in TCM.
Hi Ronan and the forum,In the same context, I would like to know the behaviour of the system in the following scenario.What will happen if I configure a TCM after loading some data in that same region ?For example, I am loading some content at this address 0x00000000.Then, I am configuring ATCM region register to configure the same address (0x00000000).Here, what will happen to the content which I loaded before configuring TCM ?Thanks,
I believe the TCM memory would take precedence.