Hi folks,
The technical reference states that only a subset of possible AXI transactions are actually generated.
This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html
What happens for this table if the master interface isn't a 64-bit AXI interface but a 32-bit one?
Is a WRAP4 transactions converted to a WRAP8 one?
Best regards,
Martin
Hello Martin,
according to the Figure1 (on page 5) of your attachment, the Cortex-A9 of Zynq-7000 has 3 AXI master ports.
There are tow 64 bit ports and one 32 bit port.
I don't know why there are 3 master ports but I guess the 2 master ports of the Cortex-A9 are hidden in the MPU module and 3 master ports of the block diagram will generate in the module.
Yasuhiko Koumoto.
Hello Robert,
I think WRAP4 of Cortex-A9 would be converted to WRAP8.
However, it will depend on the intermediate AIX64-to-AIX32 bridge.
I'm not sure how the Zynq-7000 32bit AXI is implemented.
By the way, WRAP8 of Cortex-A9 is only used for the cache line-fill.
Is your peripheral device a normal memory device?
Otherwise, I am afraid the device does not accept the WRAP transaction.
the below is referred from Figure 5-1 of "Zynq-7000 All Programmable SoC Technical Reference Manual" http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf .
You can find the AXI interconnect scheme in it.
Two AXI master ports of Cortex-A9 are connected to the On-chip RAM and L2 Cache Controller.
Therefore WRAP4 transaction from Cortex-A9 would not propagate to the other AXI interconnects.
Hi Yasuhiko,
Yes, that's right. There are two internal 64-Bit AXI interfaces.
However, the interesting question is now which transactions are generated if I have a peripheral on the accessible 32-bit AXI bus.
Will it merge the transactions? e.g. a WRAP4 is transformed to a WRAP8?
My device is a "memory"-device and is capable handling wrapped bursts.
If I connect such a device to S_AXI_GO[1:0], I assume to get wrapped bursts, because there is a connection between the L2-Cache-Controller via the 32-bit "Master Interconnect for Slave Peripherals".
L2-Cache controller will generate wrapped bursts when filling an instruction cache line.
You're talking about external device so ?
according to the Zynq-7000 TRM, L2 cache controller is compliant to the L2CC PL310.
However, such the configuration (i.e. one 64bit slave, one 64bit master and one 32bit master) as the Zynq-7000 might be impossible by the original PL310.
Therefore, I cannot imagine whether the L2 cache controller issue WRAP transaction.
If you did prepare it, there would be no problem.