Hi folks,
The technical reference states that only a subset of possible AXI transactions are actually generated.
This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html
What happens for this table if the master interface isn't a 64-bit AXI interface but a 32-bit one?
Is a WRAP4 transactions converted to a WRAP8 one?
Best regards,
Martin
Hi Yasuhiko,
My device is a "memory"-device and is capable handling wrapped bursts.
If I connect such a device to S_AXI_GO[1:0], I assume to get wrapped bursts, because there is a connection between the L2-Cache-Controller via the 32-bit "Master Interconnect for Slave Peripherals".
L2-Cache controller will generate wrapped bursts when filling an instruction cache line.
You're talking about external device so ?
Hello Martin,
according to the Zynq-7000 TRM, L2 cache controller is compliant to the L2CC PL310.
However, such the configuration (i.e. one 64bit slave, one 64bit master and one 32bit master) as the Zynq-7000 might be impossible by the original PL310.
Therefore, I cannot imagine whether the L2 cache controller issue WRAP transaction.
If you did prepare it, there would be no problem.
Yasuhiko Koumoto.