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Supported AXI transfers on Cortex-A9?

Martin Trummer

Hi folks,

The technical reference states that only a subset of possible AXI transactions are actually generated.

This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

What happens for this table if the master interface isn't a 64-bit AXI interface but a 32-bit one?

Is a WRAP4 transactions converted to a WRAP8 one?

Best regards,

Martin

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  • 0 in reply to Martin Trummer

    Hello Robert,


    I think WRAP4 of Cortex-A9 would be converted to WRAP8.

    However, it will depend on the intermediate AIX64-to-AIX32 bridge.

    I'm not sure how the Zynq-7000 32bit AXI is implemented.

    By the way, WRAP8 of Cortex-A9 is only used for the cache line-fill.

    Is your peripheral device a normal memory device?

    Otherwise, I am afraid the device does not accept the WRAP transaction.

    Best regards,

    Yasuhiko Koumoto.

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  • 0 in reply to Martin Trummer

    Hello Robert,


    I think WRAP4 of Cortex-A9 would be converted to WRAP8.

    However, it will depend on the intermediate AIX64-to-AIX32 bridge.

    I'm not sure how the Zynq-7000 32bit AXI is implemented.

    By the way, WRAP8 of Cortex-A9 is only used for the cache line-fill.

    Is your peripheral device a normal memory device?

    Otherwise, I am afraid the device does not accept the WRAP transaction.

    Best regards,

    Yasuhiko Koumoto.

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