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Supported AXI transfers on Cortex-A9?

Martin Trummer

Hi folks,

The technical reference states that only a subset of possible AXI transactions are actually generated.

This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

What happens for this table if the master interface isn't a 64-bit AXI interface but a 32-bit one?

Is a WRAP4 transactions converted to a WRAP8 one?

Best regards,

Martin

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  • 0 in reply to Martin Trummer

    Hello Martin,

    according to the Zynq-7000 TRM, L2 cache controller is compliant to the L2CC PL310.

    However, such the configuration (i.e. one 64bit slave, one 64bit master and one 32bit master) as the Zynq-7000 might be impossible by the original PL310.

    Therefore, I cannot imagine whether the L2 cache controller issue WRAP transaction.

    If you did prepare it, there would be no problem.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • 0 in reply to Martin Trummer

    Hello Martin,

    according to the Zynq-7000 TRM, L2 cache controller is compliant to the L2CC PL310.

    However, such the configuration (i.e. one 64bit slave, one 64bit master and one 32bit master) as the Zynq-7000 might be impossible by the original PL310.

    Therefore, I cannot imagine whether the L2 cache controller issue WRAP transaction.

    If you did prepare it, there would be no problem.

    Best regards,

    Yasuhiko Koumoto.

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