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On Cortex v7M architecture, looking at the T3 and T4 encodings for the B and Bcc instructions in the architecture reference manual...
Do T3 and T4 really have the J bits of the immediate value in the opposite order from one another?
T3 (20 bit immediate value): imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);T4 (24bit immediate value): I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);All the references are consistent, but it just seems particularly odd.Is there some more intuitive way to look at the Not(S xor Jn) part of the instructions?
T3 (20 bit immediate value): imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);
T4 (24bit immediate value): I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);