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On Cortex v7M architecture, looking at the T3 and T4 encodings for the B and Bcc instructions in the architecture reference manual...
Do T3 and T4 really have the J bits of the immediate value in the opposite order from one another?
T3 (20 bit immediate value): imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);T4 (24bit immediate value): I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);All the references are consistent, but it just seems particularly odd.Is there some more intuitive way to look at the Not(S xor Jn) part of the instructions?
T3 (20 bit immediate value): imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);
T4 (24bit immediate value): I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
WestfW said: don't think I trust my assembler (gas):
*rotfl*
It would be serious if "gas" produces wrong op-codes from such a standard mnemonics.
True. I probably meant "I'm not sure I understand how to get the assembler to generate the instructions I think it should." The format above "B . + immConstant*2 + 4" seems to be it...Although, you could go a long time with errors in the encoding or documentation of the J bits for B instruction on most Cortex-M processors - that's the range beyond the amount of flash on most chips, and not enough to get to RAMFUNCs.
T3/T4 encoding applies to all Thumb-2 Cores, means Cortex-A,R and M. So T4 might be used. Still not clear to me, where your problem lies. The encoding of T4 is kind of weird, agree. But I fear, you won't get an answer to the "why" :-)