On Cortex v7M architecture, looking at the T3 and T4 encodings for the B and Bcc instructions in the architecture reference manual...
Do T3 and T4 really have the J bits of the immediate value in the opposite order from one another?
T3 (20 bit immediate value): imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);T4 (24bit immediate value): I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);All the references are consistent, but it just seems particularly odd.Is there some more intuitive way to look at the Not(S xor Jn) part of the instructions?
T3 (20 bit immediate value): imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32);
T4 (24bit immediate value): I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Here's correct assembly/disassembly/hand decode. It's hard to tell - the J bits look like they're in the same order, but the unconditional branch case has that possible inversion going on...
Source (both have J1:J2 == 10, hopefully): @ SJJimm6..imm11..89ABw bne .+0b010011110000111101010 + 4 @ SJJimm10..89Aimm11..89ABw b .+0b0100111100001111011001010 + 4 Disassembly and hand decode: 00008000 <_start>: @ 8000: f05e 88f5 bne.w a61ee <_stack+0x261ee> @ oooo oScc ccii iiii ooJo Jiii iiii iiii @ 1111 0000 0101 1110 1000 1000 1111 0101 @ 8008: f1e1 9f65 b.w 9e9ed6 <*ABS*0x13c3d4+0x8adb02> @ oooo oSii iiii iiii ooJo Jiii iiii iiii @ 1111 0001 1110 0001 1001 1111 0110 0101