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Reason for having decouple write address, data channels in AXI4

Naveen

Can someone explain me the advantage of having decouple write address, data channels in AXI4?

In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled write address, data channels will help?

Thanks

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  • 0 in reply to Naveen

    Hi naveen,

    the write address channel and the write data channels of AXI are originally decoupled. The address channel is controlled by AWREADY and the data channel is controlled by WREADY. By this feature, write data can be issued in advance to its address. The AXI slave should receive such transaction. I think there would not be big advantages. It is the specification. I am not sure what is your intention of the question.


    Best regards,
    Yasuhiko Koumoto.

  • 0 in reply to Yasuhiko Koumoto

    Thanks Yasuhiko, I was trying to understand the reason/advantage of having this decoupled write address, write data channels in AXI4.

    Other than this do we have any other useful case in AXI4?

    By this feature, write data can be issued in advance to its address

    I don't see any advantage in single AXI master case other than above mentioned one. Does multi-master case had some advantage?

  • 0 in reply to Naveen

    Can someone help me by answering my last question?

  • +1 Arm Employee Badge in reply to Naveen

    I believe that it is simply a form of pipelining - many memory technologies require some setup time after receiving an address before you can do anything useful with data (set up a row buffer in DDR, set a block into write mode in an addressable Flash, page a block in a block based Flash, etc) - so by getting the address in there early you can improve overall performance.

    Pete