• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 5 replies
  • Subscribers 350 subscribers
  • Views 7722 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Reason for having decouple write address, data channels in AXI4

Naveen

Can someone explain me the advantage of having decouple write address, data channels in AXI4?

In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled write address, data channels will help?

Thanks

Parents Reply Children
  • +1 Arm Employee Badge in reply to Naveen

    I believe that it is simply a form of pipelining - many memory technologies require some setup time after receiving an address before you can do anything useful with data (set up a row buffer in DDR, set a block into write mode in an addressable Flash, page a block in a block based Flash, etc) - so by getting the address in there early you can improve overall performance.

    Pete