Can someone explain me the advantage of having decouple write address, data channels in AXI4?
In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled write address, data channels will help?
Thanks
Thanks Yasuhiko, I was trying to understand the reason/advantage of having this decoupled write address, write data channels in AXI4.
Other than this do we have any other useful case in AXI4?
By this feature, write data can be issued in advance to its address
I don't see any advantage in single AXI master case other than above mentioned one. Does multi-master case had some advantage?
Can someone help me by answering my last question?
I believe that it is simply a form of pipelining - many memory technologies require some setup time after receiving an address before you can do anything useful with data (set up a row buffer in DDR, set a block into write mode in an addressable Flash, page a block in a block based Flash, etc) - so by getting the address in there early you can improve overall performance.
Pete