• State Accepted Answer
  • Locked Locked
  • Replies 6 replies
  • Subscribers 349 subscribers
  • Views 8369 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Are simultaneous accesses to both ITCM and DTCM of Cortex-M7 possible?

Yasuhiko Koumoto

Hi experts and ARM designers,

I have found "ARM® Cortex®-M7 Processor Technical Reference Manual Revision r0p2" on the ARM site. By reading it I have a question. "Figure 1-3 Cortex-M7 functional diagram" shows all TCM accesses go through TCU. Does this mean CPU cannot access both ITCM and DTCM simultaneously? If it is correct, to locate DATA in DTCM is not useful in the performance view point because such accesses cannot be the Harvard Architecture. Is my understanding correct?

Best regards,
Yasuhiko Koumoto.

Parents
  • 0 in reply to Peter Harris

    Hi Peter and all,

    I have found the following statements in the Cortex-M7 Technical Reference Manual.

    5.7.3 TCM arbitration


    Each TCM interface receives requests from the LSU, PFU, and AHBS. In most cases, the LSU has the highest priority, followed by the PFU, with the AHBS interface having lowest priority.
    When a higher-priority device is accessing a TCM interface, an access from a lower-priority device stalls.

    From the statements, the concurrent access to both ITCM and DTCM seems to be impossible. Can anyone confirm it?

    Best regards,
    Yasuhiko Koumoto.

Reply
  • 0 in reply to Peter Harris

    Hi Peter and all,

    I have found the following statements in the Cortex-M7 Technical Reference Manual.

    5.7.3 TCM arbitration


    Each TCM interface receives requests from the LSU, PFU, and AHBS. In most cases, the LSU has the highest priority, followed by the PFU, with the AHBS interface having lowest priority.
    When a higher-priority device is accessing a TCM interface, an access from a lower-priority device stalls.

    From the statements, the concurrent access to both ITCM and DTCM seems to be impossible. Can anyone confirm it?

    Best regards,
    Yasuhiko Koumoto.

Children
  • 0 in reply to Yasuhiko Koumoto

    Hi all.

    I have misunderstood Cortex-R specifications. In the Cortex-R5 case, it has the same arbitration scheme as Cortex-M7. Therefore Cortex-R and Cortex-M7 cannot make concurrent accesses to both ITCM and DTCM. To the contrary, the legacy ARM (such as ARM9 or ARM11) could make concurrent accesses to both ITCM and DTCM, I think. It is why the paths from PFU to ITCM and from LSU to DTCM are individual.

    Best regards,
    Yasuhiko Koumoto.

  • 0 Arm Employee Badge in reply to Yasuhiko Koumoto

    Hi Yasuhiko,

    Depends on what you mean by simultaneous accesses, the following accesses can happen in parallel:

    -PFU access to I-TCM

    -LSU access to D0/1-TCM

    In the TRM statement you quoted, please note the word "each":

    Each TCM interface receives requests from the LSU, PFU, and AHBS.

    So I-TCM has an arbiter that deal with multiple accesses, and same for D0/1-TCM which has a separated arbiter.

    What you cannot do is

    - PFU (instruction fetch) and LSU (data accesses) both access to I-TCM in the same cycle, or

    - PFU and LSU both access to D0/1-TCM in the same cycle

    regards,

    Joseph

  • 0 in reply to Joseph Yiu

    Hi Joseph,

    thank you for your clarification. I was relieved. Cortex-M7 is great.

    Best regards,

    Yasuhiko Koumoto.