Hi experts and ARM designers,
I have found "ARM® Cortex®-M7 Processor Technical Reference Manual Revision r0p2" on the ARM site. By reading it I have a question. "Figure 1-3 Cortex-M7 functional diagram" shows all TCM accesses go through TCU. Does this mean CPU cannot access both ITCM and DTCM simultaneously? If it is correct, to locate DATA in DTCM is not useful in the performance view point because such accesses cannot be the Harvard Architecture. Is my understanding correct?
Best regards,Yasuhiko Koumoto.
Hi all.
I have misunderstood Cortex-R specifications. In the Cortex-R5 case, it has the same arbitration scheme as Cortex-M7. Therefore Cortex-R and Cortex-M7 cannot make concurrent accesses to both ITCM and DTCM. To the contrary, the legacy ARM (such as ARM9 or ARM11) could make concurrent accesses to both ITCM and DTCM, I think. It is why the paths from PFU to ITCM and from LSU to DTCM are individual.