Hi all,
recently I did some measurements concerning the SysTick-Timer and consumend clock cycles (because of performance reasons).
I wrote a simple function in assembly, which gets called from a C file. Before and after the call i read the value of the SysTick-Timer to determine the cycles neeed for loading the parameter value into register r0, the call and all the assembly code in the function.
Taking into account, that two consecutive (simple) LDR instructions can get pipeplined, it seems they don't get pipelined - at least when looking at the clock cycles.
Am I right assuming that loads to different memory regions (for SysTick-Timer and stack) don't get (ever) pipelined ? And maybe a slightly other question: do loads get pipelined when crossing boundaries concerning "minimum memory part sizes" (AHB-Lite) in the same memory region?
Thanks in advance,
Alex
Hi Alex,
Thanks for the dis-assembly code. Makes things clearer. Firstly, since I assume you are subtracting the first SysTick value from the second, I am not sure the cycle count obtained after this subtraction includes the time taken by the first SysTick LDR instruction. Also, I suspect the use of the BL and the BX instructions (between the load parameter instruction and the second load SysTick instruction) brings about a whole lot of cycle-computation complexity into the picture. Could you please try two LDRs without a BL and BX instruction following them and between two SysTicks loads? Hope I make sense.
Regards,
Sadanand
Hi Sadanand,
sorry for the late reply, the last days were quite busy, I'll post my results ASAP.
Alright, I finally had the time to try your suggested actions.
Firstly, since I assume you are subtracting the first SysTick value from the second, I am not sure the cycle count obtained after this subtraction includes the time taken by the first SysTick LDR instruction.
I agree with you, that the cycle count of the first SysTick LDR instruction isn't included, but that's a thing I'm aware of and, in my case, it would be the desired behaviour, anyway.
I wrote the assembly below with R0 initially containing the address of the systick->value reg, R2 and R3 initially containing the addresses to 2 different variables on the stack.
LDR R1, [R0] ;read systick val reg
LDR R2, [R2] ;read variable 1
LDR R3, [R3] ;read variable 2
LDR R0, [R0] ;read systick val reg
SUB R0, R1, R0 ;subtract second read value from first read value
The result of the SUB instruction is 5, which in my opinion only can happen, when the two loads of the stack variables get pipelined and the loads of the systick val register don't get pipelined with the variable accesses, which brings me back to my assumption, that loads to PPB memory region and System memory region don't get pipelined. What do you think?
I think there might be some traps in the mentioned code.
I agree; some pipelining must have happened, otherwise all instructions would take two clock cycles, and that would result in a final value of 6 clock cycles.
But since you're getting 5 clock cycles, it might be more 'accurate' to do the following:
SUB R4,R5,R6 ;dummy instruction to flush the pipeline
; LDR R2, [R2] ;read variable 1
; LDR R3, [R3] ;read variable 2
Now you'll be able to disable the two LDR instructions in the centre, then measure it, enable one of them, measure this one, enable both and measure both.
I wish I could give you a definitive answer, though.
Thanks for the experimentation. Much as I understand what you observe, I do feel there is a difference between the CPU clock (HCLK) and the SysTick clock that is causing the number of cycles taken to show up as 5. The Reference Manual for the STM32L152xx family (http://www.st.com/web/en/resource/technical/document/reference_manual/CD00240193.pdf) may help to sort this out.
Generally speaking: Would it be (more) accurate to set up a timer that follows CCLK and read the Timer-Counter value before beginning and after ending the test, as long as all interrupts are disabled ?
I believe so. For if you take a look at the reference manual, it mentions the SysTick clock is set to 4 MHz or Max HCLK/8, where HCLK can take up a frequency from 2 to 32 MHz depending on user configuration.
thank you for your responses.
Concerning jensbauer's suggested measurements with disabling the 2 loads:
The suggested code shows a cycle count of 4 with the 2 loads disabled, 6 cycles with just one load disabled and 7 when executing the loads in the middle, which show expected and reasonable results.
Concerning Sadanand's post relating the clock source for the SysTick-Timer:
Thanks for pointing that out. My first thought was that I could have overseen that. A view in the Programming Manual of the controller and my initialisation code reminded me that I had taken care of that already. Because the SysTick Control Register allows selecting the clock source between AHB/8 and processor clock (AHB), I guess that it shouldn't make a difference using the SysTick-Timer or a dedicated timer/counter (since in my case processor clock / AHB clock are the same / no prescaler is used).
For now, I have to stop the investigation on why these loads show the discussed behaviour because of lacking time and settle with the knowledge that the loads don't get pipelined.
Anyway, I really apprechiate your help, thank you very much.
> Concerning jensbauer's suggested measurements with disabling the 2 loads:
> The suggested code shows a cycle count of 4 with the 2 loads disabled, 6 cycles with just one load disabled and 7 when executing the loads in the middle, which show expected and reasonable results.
I suggested the dummy instructions, in order to get accurate measurements; in other words to "synchronize", so you do not get your results disturbed by the reading of the cycle counter.
If 4 cycles are being used with no loads enabled and 6 cycles are being used with 1 load enabled, that suggests the first load takes 2 clock cycles, correct ?
If 6 cycles are being used with one load enabled and 7 cycles are being used with 2 loads enabled, that suggests the second load takes 1 clock cycle, correct ?
If the above is true, then I believe the second instruction is being pipelined as expected.
-Or do I misinterpret the results ?
If you need to measure if the reading of the cycle-counter affects the pipelining, you could make a duplicate load:
LDR R1,[R0] ;read systick val reg
; LDR R4,[R0] ;dummy read of systick val reg
; LDR R2,[R2] ;read variable 1
; LDR R3,[R3] ;read variable 2
LDR R0,[R0] ;read systick val reg
SUB R0,R1,R0 ;subtract second read value from first read value
If enabling all 3 loads, I would expect the result to be...
Note: Remember that the first load in a sequence is never pipelined, so the first load will always use 2 clock cycles...
Sorry for the delay on this...
The SysTick timer is in a Strongly Ordered memory space, so the transfers to SysTick cannot pipelined with other memory accesses. For your instruction sequence, only the two reads to the variables 1 & 2 can be pipelined.
regards,
Joseph