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Cortex-M3 pipelining of consecutive LDR instructions to different memory regions?

Alexander Brunner

Hi all,

recently I did some measurements concerning the SysTick-Timer and consumend clock cycles (because of performance reasons).

I wrote a simple function in assembly, which gets called from a C file. Before and after the call i read the value of the SysTick-Timer to determine the cycles neeed for loading the parameter value into register r0, the call and all the assembly code in the function.

Taking into account, that two consecutive (simple) LDR instructions can get pipeplined, it seems they don't get pipelined - at least when looking at the clock cycles.

Am I right assuming that loads to different memory regions (for SysTick-Timer and stack) don't get (ever) pipelined ? And maybe a slightly other question: do loads get pipelined when crossing boundaries concerning "minimum memory part sizes" (AHB-Lite) in the same memory region?

Thanks in advance,

Alex

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  • 0 in reply to Alexander Brunner

    I think there might be some traps in the mentioned code.

    I agree; some pipelining must have happened, otherwise all instructions would take two clock cycles, and that would result in a final value of 6 clock cycles.

    But since you're getting 5 clock cycles, it might be more 'accurate' to do the following:

        LDR R1, [R0]     ;read systick val reg

        SUB R4,R5,R6  ;dummy instruction to flush the pipeline

    ;    LDR R2, [R2]     ;read variable 1

    ;    LDR R3, [R3]     ;read variable 2

        SUB R4,R5,R6  ;dummy instruction to flush the pipeline

        LDR R0, [R0]     ;read systick val reg

      

        SUB R0, R1, R0     ;subtract second read value from first read value

    Now you'll be able to disable the two LDR instructions in the centre, then measure it, enable one of them, measure this one, enable both and measure both.

    I wish I could give you a definitive answer, though.

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  • 0 in reply to Alexander Brunner

    I think there might be some traps in the mentioned code.

    I agree; some pipelining must have happened, otherwise all instructions would take two clock cycles, and that would result in a final value of 6 clock cycles.

    But since you're getting 5 clock cycles, it might be more 'accurate' to do the following:

        LDR R1, [R0]     ;read systick val reg

        SUB R4,R5,R6  ;dummy instruction to flush the pipeline

    ;    LDR R2, [R2]     ;read variable 1

    ;    LDR R3, [R3]     ;read variable 2

        SUB R4,R5,R6  ;dummy instruction to flush the pipeline

        LDR R0, [R0]     ;read systick val reg

      

        SUB R0, R1, R0     ;subtract second read value from first read value

    Now you'll be able to disable the two LDR instructions in the centre, then measure it, enable one of them, measure this one, enable both and measure both.

    I wish I could give you a definitive answer, though.

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