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Cortex-M3 pipelining of consecutive LDR instructions to different memory regions?

Alexander Brunner

Hi all,

recently I did some measurements concerning the SysTick-Timer and consumend clock cycles (because of performance reasons).

I wrote a simple function in assembly, which gets called from a C file. Before and after the call i read the value of the SysTick-Timer to determine the cycles neeed for loading the parameter value into register r0, the call and all the assembly code in the function.

Taking into account, that two consecutive (simple) LDR instructions can get pipeplined, it seems they don't get pipelined - at least when looking at the clock cycles.

Am I right assuming that loads to different memory regions (for SysTick-Timer and stack) don't get (ever) pipelined ? And maybe a slightly other question: do loads get pipelined when crossing boundaries concerning "minimum memory part sizes" (AHB-Lite) in the same memory region?

Thanks in advance,

Alex

Parents Reply Children
  • 0 in reply to Sadanand Gulwadi

    Generally speaking: Would it be (more) accurate to set up a timer that follows CCLK and read the Timer-Counter value before beginning and after ending the test, as long as all interrupts are disabled ?

  • 0 in reply to Jens Bauer

    I believe so. For if you take a look at the reference manual, it mentions the SysTick clock is set to 4 MHz or Max HCLK/8, where HCLK can take up a frequency from 2 to 32 MHz depending on user configuration.

  • 0 in reply to Sadanand Gulwadi

    Hi all,

    thank you for your responses.

    Concerning jensbauer's suggested measurements with disabling the 2 loads:

    The suggested code shows a cycle count of 4 with the 2 loads disabled, 6 cycles with just one load disabled and 7 when executing the loads in the middle, which show expected and reasonable results.

    Concerning  Sadanand's post relating the clock source for the SysTick-Timer:

    Thanks for pointing that out. My first thought was that I could have overseen that. A view in the Programming Manual of the controller and my initialisation code  reminded me that I had taken care of that already. Because the SysTick Control Register allows selecting the clock source between AHB/8 and processor clock (AHB), I guess that it shouldn't make a difference using the SysTick-Timer or a dedicated timer/counter (since in my case processor clock / AHB clock are the same / no prescaler is used).

    For now, I have to stop the investigation on why these loads show the discussed behaviour because of lacking time and settle with the knowledge that the loads don't get pipelined.

    Anyway, I really apprechiate your help, thank you very much.

    Regards,

    Alex

  • 0 in reply to Alexander Brunner

    > Concerning jensbauer's suggested measurements with disabling the 2 loads:

    > The suggested code shows a cycle count of 4 with the 2 loads disabled, 6 cycles with just one load disabled and 7 when executing the loads in the middle, which show expected and reasonable results.

    I suggested the dummy instructions, in order to get accurate measurements; in other words to "synchronize", so you do not get your results disturbed by the reading of the cycle counter.

    If 4 cycles are being used with no loads enabled and 6 cycles are being used with 1 load enabled, that suggests the first load takes 2 clock cycles, correct ?

    If 6 cycles are being used with one load enabled and 7 cycles are being used with 2 loads enabled, that suggests the second load takes 1 clock cycle, correct ?

    If the above is true, then I believe the second instruction is being pipelined as expected.

    -Or do I misinterpret the results ?

    If you need to measure if the reading of the cycle-counter affects the pipelining, you could make a duplicate load:

        LDR R1,[R0]     ;read systick val reg

        SUB R4,R5,R6    ;dummy instruction to flush the pipeline

    ;   LDR R4,[R0]     ;dummy read of systick val reg

    ;   LDR R2,[R2]     ;read variable 1

    ;   LDR R3,[R3]     ;read variable 2

        SUB R4,R5,R6    ;dummy instruction to flush the pipeline

        LDR R0,[R0]     ;read systick val reg

        SUB R0,R1,R0    ;subtract second read value from first read value

    If enabling all 3 loads, I would expect the result to be...

    • 8 if an instruction can be pipelined after reading the systick value.
    • 9 if an instruction cannot be pipelined after reading the systick value.

    Note: Remember that the first load in a sequence is never pipelined, so the first load will always use 2 clock cycles...

  • 0 Arm Employee Badge in reply to Jens Bauer

    Sorry for the delay on this...

    The SysTick timer is in a Strongly Ordered memory space, so the transfers to SysTick cannot pipelined with other memory accesses. For your instruction sequence, only the two reads to the variables 1 & 2 can be pipelined.

    regards,

    Joseph