Cortex-M3 pipelining of consecutive LDR instructions to different memory regions?

> Concerning jensbauer's suggested measurements with disabling the 2 loads:

> The suggested code shows a cycle count of 4 with the 2 loads disabled, 6 cycles with just one load disabled and 7 when executing the loads in the middle, which show expected and reasonable results.

I suggested the dummy instructions, in order to get accurate measurements; in other words to "synchronize", so you do not get your results disturbed by the reading of the cycle counter.

If 4 cycles are being used with no loads enabled and 6 cycles are being used with 1 load enabled, that suggests the first load takes 2 clock cycles, correct ?

If 6 cycles are being used with one load enabled and 7 cycles are being used with 2 loads enabled, that suggests the second load takes 1 clock cycle, correct ?

If the above is true, then I believe the second instruction is being pipelined as expected.

-Or do I misinterpret the results ?

If you need to measure if the reading of the cycle-counter affects the pipelining, you could make a duplicate load:

    LDR R1,[R0]     ;read systick val reg

    SUB R4,R5,R6    ;dummy instruction to flush the pipeline

;   LDR R4,[R0]     ;dummy read of systick val reg

;   LDR R2,[R2]     ;read variable 1

;   LDR R3,[R3]     ;read variable 2

    SUB R4,R5,R6    ;dummy instruction to flush the pipeline

    LDR R0,[R0]     ;read systick val reg

    SUB R0,R1,R0    ;subtract second read value from first read value

If enabling all 3 loads, I would expect the result to be...

• 8 if an instruction can be pipelined after reading the systick value.
• 9 if an instruction cannot be pipelined after reading the systick value.

Note: Remember that the first load in a sequence is never pipelined, so the first load will always use 2 clock cycles...

> Concerning jensbauer's suggested measurements with disabling the 2 loads:

> The suggested code shows a cycle count of 4 with the 2 loads disabled, 6 cycles with just one load disabled and 7 when executing the loads in the middle, which show expected and reasonable results.

I suggested the dummy instructions, in order to get accurate measurements; in other words to "synchronize", so you do not get your results disturbed by the reading of the cycle counter.

If 4 cycles are being used with no loads enabled and 6 cycles are being used with 1 load enabled, that suggests the first load takes 2 clock cycles, correct ?

If 6 cycles are being used with one load enabled and 7 cycles are being used with 2 loads enabled, that suggests the second load takes 1 clock cycle, correct ?

If the above is true, then I believe the second instruction is being pipelined as expected.

-Or do I misinterpret the results ?

If you need to measure if the reading of the cycle-counter affects the pipelining, you could make a duplicate load:

    LDR R1,[R0]     ;read systick val reg

    SUB R4,R5,R6    ;dummy instruction to flush the pipeline

;   LDR R4,[R0]     ;dummy read of systick val reg

;   LDR R2,[R2]     ;read variable 1

;   LDR R3,[R3]     ;read variable 2

    SUB R4,R5,R6    ;dummy instruction to flush the pipeline

    LDR R0,[R0]     ;read systick val reg

    SUB R0,R1,R0    ;subtract second read value from first read value

If enabling all 3 loads, I would expect the result to be...

• 8 if an instruction can be pipelined after reading the systick value.
• 9 if an instruction cannot be pipelined after reading the systick value.

Note: Remember that the first load in a sequence is never pipelined, so the first load will always use 2 clock cycles...

Sorry for the delay on this...

The SysTick timer is in a Strongly Ordered memory space, so the transfers to SysTick cannot pipelined with other memory accesses. For your instruction sequence, only the two reads to the variables 1 & 2 can be pipelined.

regards,

Joseph