I'd like to know the behavior of WFE and WFI regarding pending interrupts that occur prior to these instructions, on 2 different Cortex profiles. In both cases, the goal is to ensure any incoming interrupt will cause a wake-up when interrupts are masked/disabled.
- With Cortex-M and PRIMASK=1, BASEPRI=0, and SEVONPEND=1, when is the Event latch/register is set or cleared for pending interrupts before a WFE? In other words, is it ok to always leave SEVONPEND set or should it only be set just prior to WFE?
- With Cortex-A and interrupts disabled (CPSR.I=1), will interrupts that become pending prior to a WFI prevent it from suspending execution or does the interrupt have to occur after the WFI instruction has been executed to cause a wake-up event?
Thanks in advance!
Regarding Cortex-M, according to ARM Support:
"When the processor executes WFE instruction, it will check if the Event Register is set or not,
if set, the WFE instruction clears the Event Register, and then execute the instruction
following the WFE instruction. If cleared, the processor will enter low-power state."
"The Event Register can only be cleared by executing the WFE instruction, so it is not affected
even when all exceptions have been handled before a WFE instruction."
"In addition, you should note that the processor would not always enter sleep mode
with only one WFE instruction due to Event Register, and thus we recommend that the WFI
instruction is put in a conditional loop."
"Since an exception has been pending, the Event Register should be set until the first WFE
instruction is executed. The second WFE instruction should enable processor to enter low power
state if the Event Register is not set again by any events (or no events occur) when the second
WFE instruction is executed."
Therefore, the Event Register is set whenever a WFE wake-up event occurs (such as a pending interrupt when SEVONPEND is set) and is not cleared until WFE is executed.