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Support for pipelining flops in AXI

Naveen

Hi All,

Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible?

Thanks

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  • 0 in reply to Xingguang Feng

    Hi Feng,

    I read the BP130 datasheet, and it mention there are full registered and registered forward path two modes in RegSliceAxi.

    Do you know which document have detail block logic diagram of RegSliveAxi or where I could find them. Trying to understand all the signals timing relationship after enable these modes between address, data, contorl, valid and ready signals.

    Thanks, Tommy

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  • 0 in reply to Xingguang Feng

    Hi Feng,

    I read the BP130 datasheet, and it mention there are full registered and registered forward path two modes in RegSliceAxi.

    Do you know which document have detail block logic diagram of RegSliveAxi or where I could find them. Trying to understand all the signals timing relationship after enable these modes between address, data, contorl, valid and ready signals.

    Thanks, Tommy

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