Support for pipelining flops in AXI

Hello naveen,

>Yes, I am asking about inserting retiming flops.

OK! Thank you!

>Does master need to take special care when we have retime-flops?

No.

>First of all do we support these retiming flops?

Yes.

>When we put 1 flop in between "ready" signal connection from slave-master then master should

>wait for 1 extra cycle to see whether slave is actually finished the transaction or not.

A register slice (or a retiming flop) is not just as simple as a single DFF that delays the input by one cycle.

A register slice can be divided into 3 types:

- Full register slice: Breaks timing in both VALID and READY directions.

- Forward register slice: Breaks timing in the forward direction (i.e. VALID and payload).

- Reverse register slice: Breaks timing in the reverse direction (i.e. READY).

Looking at a full register slice:

It would have two sets of internal DFFs and an output MUX. On the input side, it performs valid/ready handshaking with the master to write a transfer into either set. On the output side, it performs the same type of valid/ready handshaking with the downstream component to issue any internal data. The handshaking on the two sides are independent. As long as either RegA or RegB is free, ready_slv would be HIGH. As long as either RegA or RegB has valid data, valid_mst would be HIGH. There are no combinatorial paths on either directions of the channel, thus it can fully break the timing.

Similarly, a forward register slice breaks timing in the forward direction, but there exists combinatorial paths in the READY direction. The same principle applies to the reverse register slice.

In the past, ARM offered standalone register slice IPs. But now they have been integrated into configurable interconnect products such as NIC-400.

Best regards,

Xingguang

Hello naveen,

>Yes, I am asking about inserting retiming flops.

OK! Thank you!

>Does master need to take special care when we have retime-flops?

No.

>First of all do we support these retiming flops?

Yes.

>When we put 1 flop in between "ready" signal connection from slave-master then master should

>wait for 1 extra cycle to see whether slave is actually finished the transaction or not.

A register slice (or a retiming flop) is not just as simple as a single DFF that delays the input by one cycle.

A register slice can be divided into 3 types:

- Full register slice: Breaks timing in both VALID and READY directions.

- Forward register slice: Breaks timing in the forward direction (i.e. VALID and payload).

- Reverse register slice: Breaks timing in the reverse direction (i.e. READY).

Looking at a full register slice:

It would have two sets of internal DFFs and an output MUX. On the input side, it performs valid/ready handshaking with the master to write a transfer into either set. On the output side, it performs the same type of valid/ready handshaking with the downstream component to issue any internal data. The handshaking on the two sides are independent. As long as either RegA or RegB is free, ready_slv would be HIGH. As long as either RegA or RegB has valid data, valid_mst would be HIGH. There are no combinatorial paths on either directions of the channel, thus it can fully break the timing.

Similarly, a forward register slice breaks timing in the forward direction, but there exists combinatorial paths in the READY direction. The same principle applies to the reverse register slice.

In the past, ARM offered standalone register slice IPs. But now they have been integrated into configurable interconnect products such as NIC-400.

Best regards,

Xingguang

Hi Feng,

I read the BP130 datasheet, and it mention there are full registered and registered forward path two modes in RegSliceAxi.

Do you know which document have detail block logic diagram of RegSliveAxi or where I could find them. Trying to understand all the signals timing relationship after enable these modes between address, data, contorl, valid and ready signals.

Thanks, Tommy

Hello Tommy,

I believe you are talking about the Technical Overview.

That's the only BP-130 document publicly accessible from Infocenter.

Xingguang