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Ways to Tx data from Cortex R5 to A53?

Hello,

I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related documentation of it?

Thanks in advance!

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+1 42Bastian Schick over 7 years ago in reply to Zombie_Ashish

If the cache is enabled, you need to flush/invalidate it in order to exchange data between R5 and A53. Snoop logic is only in the A53 cluster (if SMP mode is active).
Or for a starter, disable cacheing for OCM RAM
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+1 42Bastian Schick over 7 years ago in reply to Zombie_Ashish

If the cache is enabled, you need to flush/invalidate it in order to exchange data between R5 and A53. Snoop logic is only in the A53 cluster (if SMP mode is active).
Or for a starter, disable cacheing for OCM RAM
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+1 Zombie_Ashish over 7 years ago in reply to 42Bastian Schick

Sorry for my delayed response. Yes Invalidating the Dcashe after every write solved this memory refresh issue.

Thanks for the suggestions.
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