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Hello,
I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related documentation of it?
Thanks in advance!
Use shared memory and interrupts for hand-shaking.
Thanks. Agree with your answer.another question: is there any BSP (R5 and A53 related) which provides inbuilt APIs for shared memory read/write? Unable to find this in programmers guide of both.
check out OpenAMP
Okay so i'm successfully able to read/write data into/from BRAM from A53 cortex. But still haven't found any solution to read/write same BRAM shared memory from R5 cortex. any clue in accessing the same BRAM start address from R5?
BRAM? What SoC do you use? A Xilinx US+ I guess. BRAM is in the PL, why not choose something simpler like the DDRAM or the OCM RAM?
OCM is in the same (physical) address range for both the R5 and the A53. See chapter 4 in ug1085
OCM RAM works good for block memory write from both the cortex but most of the time getting stale data while reading (instead newly written data) from different cortex. am i missing any step to refresh this memory?
Note:
I'm using simple pointers to read/write to/from memory. do i need to enable/disable data cache?
If the cache is enabled, you need to flush/invalidate it in order to exchange data between R5 and A53. Snoop logic is only in the A53 cluster (if SMP mode is active).Or for a starter, disable cacheing for OCM RAM
Sorry for my delayed response. Yes Invalidating the Dcashe after every write solved this memory refresh issue.
Thanks for the suggestions.