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Ways to Tx data from Cortex R5 to A53?

Hello,

I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related documentation of it?

Thanks in advance!

Top replies

42Bastian Schick over 7 years ago +1

Use shared memory and interrupts for hand-shaking.
42Bastian Schick over 7 years ago in reply to Zombie_Ashish +1 verified

BRAM? What SoC do you use? A Xilinx US+ I guess. BRAM is in the PL, why not choose something simpler like the DDRAM or the OCM RAM? OCM is in the same (physical) address range for both the R5 and the...
Zombie_Ashish over 7 years ago in reply to 42Bastian Schick +1 verified

OCM RAM works good for block memory write from both the cortex but most of the time getting stale data while reading (instead newly written data) from different cortex. am i missing any step to refresh...