We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello,
I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related documentation of it?
Thanks in advance!
OCM RAM works good for block memory write from both the cortex but most of the time getting stale data while reading (instead newly written data) from different cortex. am i missing any step to refresh this memory?
Note:
I'm using simple pointers to read/write to/from memory. do i need to enable/disable data cache?
If the cache is enabled, you need to flush/invalidate it in order to exchange data between R5 and A53. Snoop logic is only in the A53 cluster (if SMP mode is active).Or for a starter, disable cacheing for OCM RAM
Sorry for my delayed response. Yes Invalidating the Dcashe after every write solved this memory refresh issue.
Thanks for the suggestions.