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Forums

  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 7 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    711 questions
    bill J
    While developing ISP in FVP, can the Sensor RAW file from a computer be sent to the input port of the ISP via the AVH-VSI interface? 10 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 6 months ago Arm Employee Badge
  • TOSA forum

    Tensor Operator Set Architecture (TOSA) provides a set of whole-tensor operations commonly employed by Deep Neural Networks.
    1 question
    Oliver Beirne
    RE: Forum FAQs 1 month ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 10 years ago Arm Employee Badge
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All questions in this Community
  • Not Answered

    Arm Keil MDK 6... Resources that help you to get started 0

    4981 views
    0 replies
    Started over 1 year ago
    by rkopsch Arm Employee Badge
  • Answered

    Keil V4.03 +1

    1715 views
    1 reply
    Latest over 1 year ago
    by rkopsch Arm Employee Badge
  • Not Answered

    8051 C compiler and a while-loop 0

    585 views
    0 replies
    Started over 1 year ago
    by clauswk
  • Not Answered

    Inquire about the official DMIPS/MHz value for Cortex A53. 0

    • Cortex-A53
    3266 views
    0 replies
    Started over 1 year ago
    by daehyunyoon
  • Answered

    About Mali GPU index buffer processing (group of 4 indices) +1

    • GPU Architecture
    • optimization
    • Optimization Solution
    • Mali GPUs
    • gpu
    2118 views
    1 reply
    Latest over 1 year ago
    by Peter Harris Arm Employee Badge
  • Suggested Answer

    Hi I need help with enabling/disabling process if mmu and mpu in cortex r5 and cortex a53 so that two processor application variable cant access each other memory address value and modify them 0

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    Latest over 1 year ago
    by nit_001
  • Suggested Answer

    How many cycles will CYCCNT count during CPU halt? 0

    1613 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    How to auto-vectorize fp16 loop under arm sve? 0

    • LLVM
    • GCC
    • Vectorization
    840 views
    0 replies
    Started over 1 year ago
    by yiwang
  • Answered

    Cacheable=0 vs Shareable=1 0

    • Cache coherency
    • Cortex-R5
    • Memory Protection Unit (MPU)
    2141 views
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    Filesystem is corrupted when sharing files from host to the Virtual Platform 0

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    by pooja_srre
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    • Ethos-U65
    • microNPU
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    Started over 1 year ago
    by iStarChip
  • Suggested Answer

    Problems with adding breakpoints in KEIL 0

    645 views
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    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Compiler 5 license error 0

    1860 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    question related to AxREGION in AXI 0

    974 views
    0 replies
    Started over 1 year ago
    by Harekrishna
  • Not Answered

    Exclusive Access In AXI3/4/5 0

    807 views
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    Started over 1 year ago
    by Harekrishna
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