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Servers and Cloud Computing forum
The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
101
questions
RE: ArmRAL: Wrong usage of k0 in LDPC rate matching
7 months ago
SoC Design and Simulation forum
The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
708
questions
RE: In CHI how the Slave side is giving the L-Credits to the Master Side
19 days ago
SystemReady Forum
The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
15
questions
RE: How to run ARM ACS
5 months ago
恩智浦汽车电子MCU讨论区博
4
questions
RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼
over 10 years ago
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Not Answered
Configuration to generate FIQ interrupts on ARMv8
0
15728
views
3
replies
Latest
over 5 years ago
by
Christopher Tory
Answered
ACE MakeUnique Transaction
0
21896
views
2
replies
Latest
over 5 years ago
by
RajaAC
Not Answered
What is the power consumption of a76 gpu and a77 gpu in normal state?
0
Cortex-A77
Cortex-A76
19943
views
0
replies
Started
over 5 years ago
by
Little_lan
Answered
[NIC-400 Interconnect] Remap mode
0
16177
views
2
replies
Latest
over 5 years ago
by
Hieu Ho
Not Answered
Problem with rand_r() and strnlen()
0
3436
views
2
replies
Latest
over 5 years ago
by
Andy Neil
Answered
What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail?
+1
Cortex-A55
Armv8-A
Cortex-A
24477
views
1
reply
Latest
over 5 years ago
by
Christopher Tory
Answered
MMU attributes implications on memory bandwidth
+1
23287
views
1
reply
Latest
over 5 years ago
by
Christopher Tory
Answered
I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ?
+1
AXI4
16349
views
1
reply
Latest
over 5 years ago
by
Christopher Tory
Answered
Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers.
+1
AXI4
15269
views
1
reply
Latest
over 5 years ago
by
Christopher Tory
Answered
AMBA 5 CHI Memory Attributes
0
AMBA 5 CHI
14648
views
1
reply
Latest
over 5 years ago
by
Christopher Tory
Answered
Compare the performance of In-order and Out-of-order in AXI protocol
+1
15957
views
1
reply
Latest
over 5 years ago
by
Christopher Tory
Answered
CHI protocol cache line states
+1
AMBA 5 CHI
SoC Verification
18315
views
1
reply
Latest
over 5 years ago
by
Christopher Tory
Answered
Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
0
AMBA
ACE
ACE 5
interconnect
AMBA 5
30166
views
7
replies
Latest
over 5 years ago
by
Christopher Tory
Suggested Answer
Which ARM cortex M-4/M-3 to buy for development?
0
23851
views
3
replies
Latest
over 5 years ago
by
Andy Neil
Answered
Meaning of scratch register in ARM series
+1
19916
views
1
reply
Latest
over 5 years ago
by
Ronan Synnott
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