AHB_LITE Extended address phase

First transfer data phase completes in 4th cycle and second transfer data phase in the 5th as you say, but the third transfer data phase completes in the 7th cycle (not the 6th), and the fourth transfer in the 8th cycle, again as you said.

An INCR4 burst type means that there will be 4 data transfer cycles; a NONSEQ and 3 SEQ transfers, possibly with some BUSY cycles in between these 4 data transfers.

Once those 4 data transfers have been signalled, HTRANS cannot signal SEQ as that would indicate a 5th transfer in a 4-beat burst.

So when HBURST indicates an INCR4 burst, after the 3rd SEQ transfer address phase ends HTRANS can only signal IDLE (if no new burst is starting) or NONSEQ (if a new burst is starting).

First transfer data phase completes in 4th cycle and second transfer data phase in the 5th as you say, but the third transfer data phase completes in the 7th cycle (not the 6th), and the fourth transfer in the 8th cycle, again as you said.

An INCR4 burst type means that there will be 4 data transfer cycles; a NONSEQ and 3 SEQ transfers, possibly with some BUSY cycles in between these 4 data transfers.

Once those 4 data transfers have been signalled, HTRANS cannot signal SEQ as that would indicate a 5th transfer in a 4-beat burst.

So when HBURST indicates an INCR4 burst, after the 3rd SEQ transfer address phase ends HTRANS can only signal IDLE (if no new burst is starting) or NONSEQ (if a new burst is starting).

Yes third transfer will completes in the 7th cycle  ..

Thanks for your information.

Regards

Muthuvenkatesh