Hi All ,
The following figure shows the INCR4 burst transaction.
Here the address increment is happening in each clk cycle As per AHB protocol Single outstanding address is allowed.
What are the possible adjustment has to be made for this transaction to slave accept the data properly.
Thanks & Regards
Muthuvenkatesh
Hi Colin ,
Thanks for your guidance. I have corrected the master address phase latching problem .
Below I mentioned the pic and I mentioned the each transfer ending cycle.
First transfer to address 9000_0000 will complete in 4th clk
Second transfer to address 9000_0004 will complete in 5th clk
Third transfer to address 9000_0008 will complete in 6th clk
Fourth transfer to address 9000_000c will complete in 8th clk
Now Is it as per protocol and once finished INCR4 Burst what value we need to pass in htrans ?
Please confirm the same . I am verifying ahb slave using my real driver (ahb_master_driver)
First transfer data phase completes in 4th cycle and second transfer data phase in the 5th as you say, but the third transfer data phase completes in the 7th cycle (not the 6th), and the fourth transfer in the 8th cycle, again as you said.
An INCR4 burst type means that there will be 4 data transfer cycles; a NONSEQ and 3 SEQ transfers, possibly with some BUSY cycles in between these 4 data transfers.
Once those 4 data transfers have been signalled, HTRANS cannot signal SEQ as that would indicate a 5th transfer in a 4-beat burst.
So when HBURST indicates an INCR4 burst, after the 3rd SEQ transfer address phase ends HTRANS can only signal IDLE (if no new burst is starting) or NONSEQ (if a new burst is starting).
Yes third transfer will completes in the 7th cycle ..
Thanks for your information.
Regards