Hi,
During the waited states of write access (data-phase of write access), address and control signal should be stable (include HWRITE) until HREADYOUT is high. Why the master needs to keep the address and control signals stable during the waited states including HWRITE? Since, address phase is already latched.
Why there is no direct pointer available the in specs for this point.
Thanks in advance.
There are a few points to consider here.
Firstly the AHB manager doesn't know that there will be wait states, so it must drive out controls for the next expected transfer request as soon as the address phase starts.
Secondly the manager can change the address phase control signals during a waited transfer under some circumstances. These are if the subordinate returns an ERROR response (the manager can choose to change HTRANS to IDLE, with all other address phase controls then possibly changing), or if HTRANS is currently indicating IDLE or BUSY then the manager can change this (with other address phase controls also possibly changing).
So the AHB subordinate must only sample these address phase controls when HREADY is driven high (in case the address phase controls changed as in the previous paragraph). The address phase controls are NOT usually "latched" by the subordinate at the start of the address phase.
As far as "direct pointers" in the specification are concerned, all of this is covered in various locations. Looking at the AHB5 spec (ARM IHI-0033C), section 3.7 covers when HTRANS and other address phase controls can change, as does 3.6.2 covering ERROR responses, and 4.2 stating when subordinates can sample the address phase controls.
Hi, Thank you for the detailed response. Let's assume, if the address phase of write access is completed with hreadyout high, next cycle wait state inserted by de-asserting of hreadyout low by slave, the manager is supposed to keep the hwrite stable (high) for this pending transaction? or the manger can issue next read access by de-asserting hwrite?
If I understand correctly you are describing the sort of sequence shown in figure 3-5 in the AHB5 spec, where a sequence of read and write transfers are shown (although this shows a waited read transfer, not a write).
In cycle T1-T2 we see a read address phase completing because HREADY is sampled high at T2, and then T2-T4 is the read data phase. During the T2-T4 period we have a write address phase, with HWRITE high.
So this shows that the address phase controls indicate the next transfer being requested, and they are not related to the previous transfer address phase indication which is currently completing a waited data phase.
I am refering to figure figure 3-4, Does the manager need to keep the HWRITE signal stable during the wait states(data-phase) of write access? the figure 3-4 shows the HWRITE stable (HIGHT) during the wait states. That means manager cannot change HWRITE during wait states of write transfer.
Figure 3-4 is showing just a single write transfer, with the address phase signals driven in the first cycle, and then the data phase signals in the second and third cycles (because it ws a waited transfer). HWRITE is shown as "bus stable" to use the wording in the timing diagram conventions during the write transfer data phase, because this is the expected normal behaviour for most transfers.
Remember that this section 3.1 in the protocol is introducing "Basic transfers", so at this point we are only describing basic operation of the address and data phases, and not looking at more complex (unusual) scenarios, so normally the address phase signals are held constant during a waited data phase.
I had referenced figure 3-5 as this shows a sequence of read and write transfers, so there HWRITE had a defined value rather than the undefined but stable value shown in figure 3-4.
But both diagrams correctly show HWRITE (and other address phase signals) constant during a waited transfer as this is what we would expect for the majority of transfers, especially as we are just introducing the concepts of address and data phases.
It is later in the spec when we are looking at more complex scenarios that we see occasions when the address phase controls can potentially change during waited transfers, and these are the ones I referred to in my first reply, ERROR responses and when HTRANS is indicating IDLE or BUSY.
So the only time a subordinate can safely sample the address phase controls for the next transfer are when HREADY is high, indicating the end of the current data phase transfer.