Hi,
During the waited states of write access (data-phase of write access), address and control signal should be stable (include HWRITE) until HREADYOUT is high. Why the master needs to keep the address and control signals stable during the waited states including HWRITE? Since, address phase is already latched.
Why there is no direct pointer available the in specs for this point.
Thanks in advance.
There are a few points to consider here.
Firstly the AHB manager doesn't know that there will be wait states, so it must drive out controls for the next expected transfer request as soon as the address phase starts.
Secondly the manager can change the address phase control signals during a waited transfer under some circumstances. These are if the subordinate returns an ERROR response (the manager can choose to change HTRANS to IDLE, with all other address phase controls then possibly changing), or if HTRANS is currently indicating IDLE or BUSY then the manager can change this (with other address phase controls also possibly changing).
So the AHB subordinate must only sample these address phase controls when HREADY is driven high (in case the address phase controls changed as in the previous paragraph). The address phase controls are NOT usually "latched" by the subordinate at the start of the address phase.
As far as "direct pointers" in the specification are concerned, all of this is covered in various locations. Looking at the AHB5 spec (ARM IHI-0033C), section 3.7 covers when HTRANS and other address phase controls can change, as does 3.6.2 covering ERROR responses, and 4.2 stating when subordinates can sample the address phase controls.