AHB Write Strobe calculation

Hi ,

I am trying to generate strobes for narrow burst write transfers  where my size of the transfer is less than the data width of the bus

e.g I am doing a wrap16 burst transfer with HSIZE=1 (half-word transfer) HBURST = 6

-> I have calculated the wrap boundary and upper limit as mentioned in the protocol specification

-> If my starting address is 0x30 , then the next address would become 0x32 and it follows like

     0x30 -> 0x32 ->0x34->0x36->0x38->0x40 ...

i)According to ahb protocol specification in section 3.5.2 it mentioned calculating strobe according to address offset and size which means
  for address 0x30 -> lower 2 bytes are active
                     0x32 -> upper 2 bytes are active
                     0x34 -> lower 2 bytes are active ....
ii) I found this logic in axi protocol spec about lower active byte lanes and upper active byte lanes
       Use these equations to determine which byte lanes to use for the first transfer in a burst:
       Lower_Byte_Lane = Start_Address - (INT(Start_Address / Data_Bus_Bytes)) x Data_Bus_Bytes
       Upper_Byte_Lane = Aligned_Address + (Number_Bytes - 1) - (INT(Start_Address / Data_Bus_Bytes)) x Data_Bus_Bytes.
       Use these equations to determine which byte lanes to use for all transfers after the first transfer in a burst:
       Lower_Byte_Lane = Address_N – (INT(Address_N / Data_Bus_Bytes))x Data_Bus_Bytes
       Upper_Byte_Lane = Lower_Byte_Lane + Number_Bytes – 1.
       Data is transferred on:
       DATA[(8 x Upper_Byte_Lane) + 7 : (8 x Lower_Byte_Lane)]

Can anyone help me out whether to use the same strobe calculation for ahb bursts or it is explicit for axi only?
Thank you.

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  • Basically yes. The AHB5 subordinate needs to look at HADDR, HSIZE and HWSTRB to see which byte lanes contain valid data.

    So in your example, this isn't meaningless as it indicates only HWDATA[23:16] contains valid data, but it does require the transfer subordinate to look at all the control signals to determine the valid data.

    I guess the strobe requirement has been specified this way for easier connection to AHB5 systems. HWSTRB could just be tied off to 4'b1111 for an AHB5 manager that doesn't use strobes, and that would then be valid regardless of the HADDR and HSIZE values.