Hi , I am trying to generate strobes for narrow burst write transfers where my size of the transfer is less than the data width of the bus
e.g I am doing a wrap16 burst transfer with HSIZE=1 (half-word transfer) HBURST = 6-> I have calculated the wrap boundary and upper limit as mentioned in the protocol specification
-> If my starting address is 0x30 , then the next address would become 0x32 and it follows like
0x30 -> 0x32 ->0x34->0x36->0x38->0x40 ...
i)According to ahb protocol specification in section 3.5.2 it mentioned calculating strobe according to address offset and size which means for address 0x30 -> lower 2 bytes are active 0x32 -> upper 2 bytes are active 0x34 -> lower 2 bytes are active ....ii) I found this logic in axi protocol spec about lower active byte lanes and upper active byte lanes Use these equations to determine which byte lanes to use for the first transfer in a burst: Lower_Byte_Lane = Start_Address - (INT(Start_Address / Data_Bus_Bytes)) x Data_Bus_Bytes Upper_Byte_Lane = Aligned_Address + (Number_Bytes - 1) - (INT(Start_Address / Data_Bus_Bytes)) x Data_Bus_Bytes. Use these equations to determine which byte lanes to use for all transfers after the first transfer in a burst: Lower_Byte_Lane = Address_N – (INT(Address_N / Data_Bus_Bytes))x Data_Bus_Bytes Upper_Byte_Lane = Lower_Byte_Lane + Number_Bytes – 1. Data is transferred on: DATA[(8 x Upper_Byte_Lane) + 7 : (8 x Lower_Byte_Lane)] Can anyone help me out whether to use the same strobe calculation for ahb bursts or it is explicit for axi only?Thank you.
Although the strobe rules are similar for AHB5 and AXI, there are enough differences to make me suggest not using the AXI equations.
The first point is that AXI only supplies a start address for a transaction, so the equations need to base all calculations on the start address then being incremented N times, making them more complex. Whereas AHB5 is simpler in that you have an address for every transfer.
Then there is the horrible subject of endianness (horrible for me as I struggle to think of anything other than little endian). AXI is a byte invariant endian protocol, so it doesn't matter if you are looking at big or little endian transfers, the potential active byte lanes remain the same. But AHB5 supports both byte and word invariant implementations, and if you use word invariant then this changes the possible active byte lanes when comparing little and big-endian, complicating the equations.
And then just a protocol observation, AXI is strict in that you can only assert WSTRB bits that could be used as constrained by the AWADDR/AWSIZE/AWBURST transaction values, and all other WSTRB bits must be low. Whereas AHB allows HBSTRB bits outside the HADDR/HSIZE constrained range to be asserted, but they are meaningless as they won't contain valid data. I prefer the stricter AXI description in this respect as it is then clear which byte lanes are in use from just WSTRB alone.
And a comment on the addresses described at the start of your question. An INCR16 16-bit transaction starting at 0x30 will not include a transfer to 0x40. Instead the sequence would be 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e then wrapping back to 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c and finally 0x2e.
Getting back to your question, I've also never found the equations to be of much use, and instead prefer to just visualise how the possible byte lanes change in a burst. So for a 16-bit transfer on a 32-bit bus it will be HADDR[1] that will indicate which half of the data bus can be used, with HADDR[1]=0 indicating HWDATA[15:0] for a little-endian bus or a byte-invariant big-endian bus, or HWDATA[31:16] for a word invariant big-endian bus.
And remember that HADDR/HSIZE (and system endianness) define which byte lanes COULD be used, so HWSTRB could use all or some of those possible byte lanes (as well as meaninglessly asserting HBSTRB bits outside the allowed range).
so ahb master doesn't have any possible restrictions on strobe and it can send some meaningless strobes as address = 0x02 size=1(half word) and strobe=0x0111 ,Now it is slave responsibility to validate the strobes accordingly and write into registers depending on the address and size it received is it correct ?
Basically yes. The AHB5 subordinate needs to look at HADDR, HSIZE and HWSTRB to see which byte lanes contain valid data.
So in your example, this isn't meaningless as it indicates only HWDATA[23:16] contains valid data, but it does require the transfer subordinate to look at all the control signals to determine the valid data.
I guess the strobe requirement has been specified this way for easier connection to AHB5 systems. HWSTRB could just be tied off to 4'b1111 for an AHB5 manager that doesn't use strobes, and that would then be valid regardless of the HADDR and HSIZE values.