Why does the APB bus need a PENABLE signal?

Why does the APB bus need a PENABLE signal?

This topic talks about the purpose of the SETUP and ACCESS phases. Indeed, if a peripheral device responds to a request, it must first understand what is required of it and then provide the necessary data. It is clear why reading from a peripheral device requires at least two clock cycles. It is possible to explain why recording to a peripheral device is made with two cycles - for example, for uniformity. But why do we need the PENABLE signal? The standard could force developers just to leave the PSEL line at logic zero for at least two clock cycles - the effect would be the same.

The PENABLE line could be used for packet data transmission. For example, when an address is set in the SETUP state, and then several words are transmitted to this address over several cycles in the ACCESS state. But APB does not provide for such packet data transfer.

The PENABLE line could be used if the master requires a pause. But in this case, the master device can either not start the transmission (and not set the PSEL), or interrupt it, return the PSEL to logical zero, and then, when ready, set the PSEL again.

There is a feeling that the PENABLE line is redundant and has a pronounced reference character.
1) Is it possible to give an example of a situation where a data transfer operation via the APB bus is impossible using only the PSEL and PCLK lines and requires the presence of PENABLE?
2) What were the creators of the AMBA2 standard guided by when they added the PENABLE line to the APB bus?
  • To quickly answer your question, yes, PENABLE is largely redundant.

    A simple state machine could track the "idle", "setup" and "access" phases of a transfer, knowing "setup" is always a single cycle, "access" continues until PREADY is high, and "idle" is used when PSEL is low.

    PENABLE was probably in the protocol to support combinatorial interfaces, where PSEL & !PENABLE would indicate the "setup" phase when PADDR and PWRITE were sampled, and then PSEL & PENABLE would indictate when the "access" phase occurred, when latches would be open to sample PWDATA or drive PRDATA.

    In synchronous peripheral designs you can ignore PENABLE if your state machine tracks the access progression using PSEL and PREADY on PCLK rising edges, but you could still include PENABLE if you wanted.

    But PENABLE ***MUST*** be generated correctly by the APB bridge source of transfers so that peripherals can chose whether or not to use PENABLE.