Early bus termination

Sorry, my earlier replies were wrongly looking at bus master handover on the original AHB protocol using HBUSREQ and HGRANT to control the handover. You don't have any of that in an interconnect, so the interconnect itself handles all the transfer request detection and decision making as to which transfer to allow through to a slave when two or more requests are for the same target.

So where the interconnect is switching from one master source to another, the HREADY signals seen will be different at each master. HREADY going to the new master would need to initially be high so that the transfer request can be sampled, while the HREADY to the currently active master will be determined by whatever the destination slave is returning for the current data phase transfer.

It's only once the first transfer address phase from the new master has been sampled (the input stage logic in the interconnect will need to store that new transfer address phase until it can be passed through to the slave) that the arbitration logic in the interconnect can decide if the new request takes priority over the currently active master source, at which point the new master will be stalled until the current transfer from the old master can complete.

So yes, you will have different HREADY values going back to masters in the system, depending on whether the interconnect input stage for that master is able to sample a new request (HREADY high), or if a request has been sampled but cannot be routed through to the target slave yet (HREADY low), or HREADY driven by the HREADYOUT from the slave because this master is the current sources selected to access the target slave.

Hopefully I've understood your question better this time.

Sorry, my earlier replies were wrongly looking at bus master handover on the original AHB protocol using HBUSREQ and HGRANT to control the handover. You don't have any of that in an interconnect, so the interconnect itself handles all the transfer request detection and decision making as to which transfer to allow through to a slave when two or more requests are for the same target.

So where the interconnect is switching from one master source to another, the HREADY signals seen will be different at each master. HREADY going to the new master would need to initially be high so that the transfer request can be sampled, while the HREADY to the currently active master will be determined by whatever the destination slave is returning for the current data phase transfer.

It's only once the first transfer address phase from the new master has been sampled (the input stage logic in the interconnect will need to store that new transfer address phase until it can be passed through to the slave) that the arbitration logic in the interconnect can decide if the new request takes priority over the currently active master source, at which point the new master will be stalled until the current transfer from the old master can complete.

So yes, you will have different HREADY values going back to masters in the system, depending on whether the interconnect input stage for that master is able to sample a new request (HREADY high), or if a request has been sampled but cannot be routed through to the target slave yet (HREADY low), or HREADY driven by the HREADYOUT from the slave because this master is the current sources selected to access the target slave.

Hopefully I've understood your question better this time.