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Early bus termination

In the protocol it is written that when there is interconnect the slave is required to support the transition between masters.
Does it mean that the address and control signals go to another master or the data signals also.?
For example:

If the first master (green) was returned a low HREADY in the DATA PHASE (in cnt=0) , and he did not finish to write the data, is it possible to force the new master (M1) to receive a high HREADY,
and also the slave as an input, but the first master to receive the low HREADYOUT. And in fact we will move in the next clock (cnt=1)) to the DATA PHASE of the new master.

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