In the protocol it is written that when there is interconnect the slave is required to support the transition between masters.Does it mean that the address and control signals go to another master or the data signals also.?For example:If the first master (green) was returned a low HREADY in the DATA PHASE (in cnt=0) , and he did not finish to write the data, is it possible to force the new master (M1) to receive a high HREADY, and also the slave as an input, but the first master to receive the low HREADYOUT. And in fact we will move in the next clock (cnt=1)) to the DATA PHASE of the new master.
In fact I have two HREADY for the BUS one that responds to DATA (it is low above and the green master receives a low HREADY). And the second one for the next request - usually they are the same but for the situation above, at CNT=0 even if HREADY is low, the slaves and the new master will get a high HREADY because I must go to the next request in address and data phase.
The bus master handover occurs over 2 cycles, the address phase and the data phase. So you would have master#2 performing the purple address phase transfer in your diagram, while master#1 is still performing the final green transfer data phase.
If this final green data phase transfer sees a wait state, this wait state will stall both the master#1 data phase completion AND the master#2 address phase being sampled. No transfers will be lost as the wait state stalls both masters involved in the bus master handover.
Have a look at figure 3-16 in the AHB2 spec. This shows a bus master handover with wait states on the bus. You can see that HADDR changes to A at T5, but because of the wait state on the bus for the final data phase transfer from the previous master we don't see the new master's A transfer data phase start on HWDATA until T7.
The question is more complex, is it possible to split the hready in the interconnect so that the first master will receive the low hready from slave and be delayed, while the new master and the slaves will receive a high hready in order to serve the next address phase. The only thing that is a bit strange is that the slave may send a low hreadyout to the first master, and receive a high hready from the interconnect that instructs it to respond to the new send.
But it still seems to be aligned to the protocol
Sorry, my earlier replies were wrongly looking at bus master handover on the original AHB protocol using HBUSREQ and HGRANT to control the handover. You don't have any of that in an interconnect, so the interconnect itself handles all the transfer request detection and decision making as to which transfer to allow through to a slave when two or more requests are for the same target.
So where the interconnect is switching from one master source to another, the HREADY signals seen will be different at each master. HREADY going to the new master would need to initially be high so that the transfer request can be sampled, while the HREADY to the currently active master will be determined by whatever the destination slave is returning for the current data phase transfer.
It's only once the first transfer address phase from the new master has been sampled (the input stage logic in the interconnect will need to store that new transfer address phase until it can be passed through to the slave) that the arbitration logic in the interconnect can decide if the new request takes priority over the currently active master source, at which point the new master will be stalled until the current transfer from the old master can complete.
So yes, you will have different HREADY values going back to masters in the system, depending on whether the interconnect input stage for that master is able to sample a new request (HREADY high), or if a request has been sampled but cannot be routed through to the target slave yet (HREADY low), or HREADY driven by the HREADYOUT from the slave because this master is the current sources selected to access the target slave.
Hopefully I've understood your question better this time.