• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 3 replies
  • Subscribers 89 subscribers
  • Views 1882 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Question regarding IP-XACT Bus Definition of AMBA5 AHB5Initiator

kangho Lee

Hello, 

I'm kangho Lee managing IP-XACT bus definiton in my company.

I can't create issue to Contact Support (arm.com) with unknown error. so I borrow this page.

I have a question regarding IP-XACT Bus Definition of AMBA5 AHB5Initiator.

My company's engineer is provided IP and bus definition [amba.com AHB5 Initiator r0p0_0] from ARM. An AHB5Initiatior is used in that IP.

But I found that revision of bus definition is defferent with my managed one and port list and port element value are different also.

I write related information of bus definition and abstraction definition of AHB5 Initiator below.

The revision 0 and revision 2 don't have compatibility. so I think revision 0 and revision 2 are different abstraction definition but they have same VLNV [amba.com AMBA5 AHB5Initiator r0p0_0]

It's unable to change abstraction definition from revision 0 to revision 2 because Many IP are already designed IP with revision 0.

Can you confirm this?

 

Managed bus Definition New bus Definition Managed Abstraction Definition New Abstraction Definition Managed Abstraction Definition (Additional Information)
VLNV amba.com AMBA5 AHB5Initiator r0p0_0 VLNV amba.com AMBA5 AHB5Initiator_rtl r0p0_0 amba.com AMBA5 AHB5Initiator_rtl r0p1_0
arm:revision 0 2 arm:revision 0 2 0
description AHB5 initiator updated according to spec ARM IHI 0033B.b (ID102715). The bus definition is intended to use with interfaces associated with initiator device connections (those between the bus master and the interconnect). This is an update to the AHBLite features released with AMBA3. It improves memory type support (HPROT on 7 bits), HMASTLOCK can be asserted with different schemes, secured, locked and exclusive transfers are now supported with additional signals. Atomicity is also introduced. AHB5 initiator according to spec ARM IHI 0033C. The bus definition is intended to be used with interfaces associated with initiator device connections (those between the master and the interconnect).Reference: AMBA AHB Protocol Specification ARM IHI 0033C www.arm.com/.../AMBA.html port list HCLK HCLK HCLK
　 HCLKEN HCLKEN HCLKEN
　 HRESETn HRESETn HRESETn
　 HADDR HADDR HADDR
　 HBURST HBURST HBURST
　 HMASTLOCK HMASTLOCK HMASTLOCK
　 HPROT HPROT HPROT
　 HSIZE HSIZE HSIZE
　 HNONSEC HNONSEC HNONSEC
　 HEXCL HEXCL HEXCL
　 HMASTER HMASTER HMASTER
　 HTRANS HTRANS HTRANS
　 HWDATA HWRITE HWRITE
　 HWRITE HWDATA HWDATA
　 HRDATA HWSTRB HWSTRB
　 HREADYOUT HRDATA HRDATA
　 HRESP HREADY HREADY
　 HEXOKAY HRESP HREADYOUT
　 HSELx HEXOKAY HRESP
　 HREADY HAUSER HEXOKAY
　 HRUSER HWUSER HSELx
　 HWUSER HRUSER HAUSER
　 HAUSER HBUSER HWUSER
　 　 HTRANSCHK HRUSER
　 　 HADDRCHK HBUSER
　 　 HCTRLCHK1 HTRANSCHK
　 　 HCTRLCHK2 HADDRCHK
　 　 HPROTCHK HCTRLCHK1
　 　 HWSTRBCHK HCTRLCHK2
　 　 HWDATACHK HPROTCHK
　 　 HRDATACHK HWSTRBCHK
　 　 HREADYCHK HWDATACHK
　 　 HRESPCHK HRDATACHK
　 　 HAUSERCHK HREADYOUTCHK
　 　 HRUSERCHK HREADYCHK
　 　 HWUSERCHK HRESPCHK
　 　 HBUSERCHK HSELxCHK
　 　 　 HAUSERCHK
　 　 　 HRUSERCHK
　 　 　 HWUSERCHK
　 　 　 HBUSERCHK

regards, 

kangho Lee.

Parents Reply Children