We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
For the path between fclk and tck, how do I add SDC constraints? False path or max-delay?
Below are some of these pathes.
Sounds like SoC design. So you should post this in another forum.
Thanks a lot. I will move it to SoC Design forum
Done :)