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SoC Design forum
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The SoC Design community is the place to be when planning or designing your SoC. Here, we discuss design and implementation, Artisan or other physical IP, manufacturing processes and technology challenges.
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Unanswered questions
State Machine for AHB-Lite Protocol
Not Answered
16 days ago
Amba Adaptive Traffic Profiles question
Not Answered
13 days ago
[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
Answered
13 days ago
Assertion for Multiple Transfer on APB Bus
Not Answered
12 days ago
What purpose do wrapping BURST transfers serve?
Answered
16 days ago
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State Machine for AHB-Lite Protocol
0
218
views
3
replies
Latest
7 days ago
by
Colin Campbell
Not Answered
Amba Adaptive Traffic Profiles question
0
137
views
1
reply
Latest
10 days ago
by
Matteo Maria Andreozzi
Answered
[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
+1
219
views
2
replies
Latest
11 days ago
by
Zax
Not Answered
Assertion for Multiple Transfer on APB Bus
0
150
views
2
replies
Latest
11 days ago
by
Rakesh Venkatesan
Answered
What purpose do wrapping BURST transfers serve?
+1
174
views
1
reply
Latest
11 days ago
by
Colin Campbell
Answered
Can a simple processor with load-store architecture support BURST?
0
273
views
1
reply
Latest
21 days ago
by
Colin Campbell
Answered
Why does an AHB slave require HBURST signal?
0
252
views
1
reply
Latest
21 days ago
by
Colin Campbell
Answered
What purpose does BURST feature in AHB serve?
0
240
views
1
reply
Latest
21 days ago
by
Colin Campbell
Answered
How do I add AHB interface to a processor with Load Store Architecture?
0
201
views
1
reply
Latest
25 days ago
by
Colin Campbell
Suggested Answer
Is there any scenario where HWDATA and HRDATA are used simultaneously?
0
180
views
1
reply
Latest
25 days ago
by
Colin Campbell
Not Answered
ACE protocol : Eviction and snoop request at same time
0
106
views
0
replies
Started
26 days ago
by
Chakri Myneni
Not Answered
Request for advise on better ARM learning path for VLSI engineer
0
167
views
1
reply
Latest
29 days ago
by
Joseph Yiu
Not Answered
Bypassing all clock gates in Cortex-R52 (ARMv8)
0
130
views
0
replies
Started
1 month ago
by
Zack Yang
Not Answered
[ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface!
0
488
views
1
reply
Latest
1 month ago
by
Martin Weidmann
Not Answered
One question about the power pin connection on Arm Artisan 14nm 14LPP High-Speed Single-Port SRAM
0
160
views
0
replies
Started
1 month ago
by
binbin
Suggested Answer
When should APB slave Sample address/Data for read/write transaction from APB master?
0
776
views
5
replies
Latest
1 month ago
by
Colin Campbell
Not Answered
AXI 4 UPsizer Downsizer module's protocol checker Error with WSTRB?
0
370
views
2
replies
Latest
1 month ago
by
Colin Campbell
Not Answered
Is during AXI unaligned transfer not all WDATA bits used?
0
272
views
1
reply
Latest
1 month ago
by
Colin Campbell
Not Answered
When Wrapping happens in AXI?
0
343
views
1
reply
Latest
1 month ago
by
Colin Campbell
Not Answered
What is Byte Invariance
0
360
views
1
reply
Latest
1 month ago
by
Colin Campbell
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