Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
System
Jump...
Cancel
System
SoC Design forum
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
SoC Design forum
Description
The SoC Design community is the place to be when planning, designing, or researching your SoC. Here, we discuss design and implementation, Artisan or other physical IP, manufacturing processes and technology challenges.
Threads
361 Questions
Tell us what you think
Unanswered questions
Forum FAQs
2 months ago
Coresight - observe internal design signals
Not Answered
7 days ago
New member
Answered
1 month ago
APB - Purpose of PADDR?
Not Answered
1 month ago
Does it use a Slow Clock to turn off Main Clock?
Not Answered
1 month ago
More developer forums
Android forum
Arm Compilers forum
Arm Development Platforms forum
Arm Development Studio forum
Classic processors forum
Cortex-A / A-Profile forum
Cortex-M / M-Profile forum
Cortex-R / R-Profile forum
Embedded forum
GNU Toolchain forum
Graphics and Gaming forum
HPC forum
Infrastructure Solutions
Keil forum
Machine Learning forum
Morello Forum
Simulation Models forum
SoC Design forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Not Answered
Forum FAQs
0
ARM Community
3099
views
0
replies
Started
2 months ago
by
Annie Cracknell: Back on the 8th! :)
Not Answered
Coresight - observe internal design signals
0
CoreSight Architecture
83
views
0
replies
Started
7 days ago
by
SBR_123
Answered
New member
0
932
views
11
replies
Latest
27 days ago
by
Andy Neil
Not Answered
APB - Purpose of PADDR?
0
APB
APB Peripherals
AMBA 3 APB Interface
AMBA 2 APB Interface
439
views
1
reply
Latest
1 month ago
by
Colin Campbell
Not Answered
Does it use a Slow Clock to turn off Main Clock?
0
247
views
0
replies
Started
1 month ago
by
Ridge Mao
Answered
Can re-order depth affect functionality of write transaction?
0
956
views
5
replies
Latest
1 month ago
by
Colin Campbell
Not Answered
Alignment Address Calculation in AHB
+1
AMBA
AHB
Interface
11891
views
5
replies
Latest
1 month ago
by
Colin Campbell
Not Answered
HTRANS when HREADY is low on the 2nd HCLK after starting the transfer
0
AMBA 3 AHB Interface
AHB
487
views
1
reply
Latest
1 month ago
by
Colin Campbell
Answered
AMBA TLM 2.0 Library & AMBA-PV Extensions to TLM
+1
1436
views
3
replies
Latest
2 months ago
by
Toshihisa Oishi
Not Answered
Does CoreSight support ThunderX2 server?
0
CoreSight
974
views
0
replies
Started
2 months ago
by
hi-watanabe
Not Answered
How to calculate AXI interleave depth and reorder depth.
0
AXI4
2016
views
0
replies
Started
2 months ago
by
hungtaowu
Not Answered
AHB two-cycle Response
+1
2444
views
1
reply
Latest
2 months ago
by
Colin Campbell
Not Answered
Looking for manufacturer to produce our motherboard design
0
11377
views
1
reply
Latest
2 months ago
by
Ibrahim112
Not Answered
In APB, for data bus width, can I increase from 32 bits(default) to 64 bits(as per my project requirements)?
0
APB
AMBA 2 APB Interface
4051
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
what is "transfer" signal mentioned in the APB state diagram? Can I use "PSELx" signal to determine transfer is going to happen?
0
APB
AMBA 2 APB Interface
3893
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
Can secure states know that they are in secure state?
0
4041
views
0
replies
Started
3 months ago
by
chenyinhua
Not Answered
L4 cache in N1 SDP SoC
0
4477
views
2
replies
Latest
3 months ago
by
Oliver Beirne - on holiday until 1st March
Not Answered
test cases for apb
0
6856
views
4
replies
Latest
3 months ago
by
Antonetta
Answered
Number of masters/slaves in AHB
0
4366
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
L1 cache BW
0
4892
views
2
replies
Latest
4 months ago
by
fixxxer
>