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SoC Design forum
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The SoC Design community is the place to be when planning or designing your SoC. Here, we discuss design and implementation, Artisan or other physical IP, manufacturing processes and technology challenges.
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Unanswered questions
ACE protocol : Eviction and snoop request at same time
Answered
1 month ago
AXI3 write data interleaving with same AWID
Not Answered
21 days ago
AHB revisions from AHB3 to AHB5
Not Answered
11 days ago
Burst termination with BUSY transfer on AHB
Not Answered
10 days ago
Regarding retry response
Not Answered
10 days ago
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Answered
ACE protocol : Eviction and snoop request at same time
+1
331
views
1
reply
Latest
6 days ago
by
Christopher Tory
Not Answered
AXI3 write data interleaving with same AWID
0
394
views
4
replies
Latest
6 days ago
by
mveereshm622
Not Answered
AHB revisions from AHB3 to AHB5
0
146
views
1
reply
Latest
7 days ago
by
Colin Campbell
Not Answered
Burst termination with BUSY transfer on AHB
0
126
views
1
reply
Latest
7 days ago
by
Colin Campbell
Not Answered
Regarding retry response
0
118
views
1
reply
Latest
7 days ago
by
Colin Campbell
Not Answered
APB3 Slave responding when PSEL = 0
0
321
views
2
replies
Latest
11 days ago
by
vshankar11
Not Answered
What is expected from response if in WRAP txn in AHB is un-aligned.
0
101
views
1
reply
Latest
12 days ago
by
Colin Campbell
Not Answered
AMBA
0
106
views
1
reply
Latest
13 days ago
by
Colin Campbell
Answered
Does AHB-Lite Protocol require the master processor to be pipelined?
+1
149
views
1
reply
Latest
13 days ago
by
Colin Campbell
Answered
APB process when pstrb = "0000" or "0101" during write transaction
0
249
views
2
replies
Latest
18 days ago
by
Hyunkyu
Not Answered
Dealing with Inout Ports - design and testbench writing
0
93
views
0
replies
Started
24 days ago
by
Kedhar Guhan
Answered
How do I add AHB interface to a processor with Load Store Architecture?
0
407
views
2
replies
Latest
24 days ago
by
Kedhar Guhan
Not Answered
Axi4 Write Transaction
0
248
views
1
reply
Latest
27 days ago
by
vstehle
Not Answered
State Machine for AHB-Lite Protocol
0
367
views
3
replies
Latest
1 month ago
by
Colin Campbell
Not Answered
Amba Adaptive Traffic Profiles question
0
236
views
1
reply
Latest
1 month ago
by
Matteo Maria Andreozzi
Answered
[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
+1
367
views
2
replies
Latest
1 month ago
by
Zax
Not Answered
Assertion for Multiple Transfer on APB Bus
0
286
views
2
replies
Latest
1 month ago
by
Rakesh Venkatesan
Answered
What purpose do wrapping BURST transfers serve?
+1
329
views
1
reply
Latest
1 month ago
by
Colin Campbell
Answered
Can a simple processor with load-store architecture support BURST?
0
402
views
1
reply
Latest
1 month ago
by
Colin Campbell
Answered
Why does an AHB slave require HBURST signal?
0
382
views
1
reply
Latest
1 month ago
by
Colin Campbell
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