Dear Community,I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.
a) I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.When there are Bust length signals -AWLEN, ARLEN, which specifies the number of data transactions, whey we need another signal for burst size? Isn't the bust length info enough to specify how many transaction we need master to do?
b) Burst Address
Can someone please explain how AXI decides the next address of transaction in Bust mode? In the spec there is some equation, but I cannot clearly understand it.
Please see below the simulation waveform, I want to understand the Burst behavioral here:
Here the awaddr is always 0, but burst type is 1 which means we are dealing with increment burst.
The behavioral of awlen, awsize signals are not clear for me. Also awcache signal is not clear
Can someone please explain
1) How many data will be written
2) In which addresses
3) What is awcache value showing?
a) AxSIZE indicates the width of each data transfer in a transaction. AxLEN then indicate the length of the transaction, so how many data transfers there will be in the transaction.
b) AxADDR indicates the start address for a transaction. The slave being accessed then uses AxSIZE to know by how much to change the address by for each subsequent transfer in the transaction.
- for AxBURST=INCR the address will increment for each transfer in the transaction
- for AxBURST=WRAP the address will increment up to the wrap boundary for the transaction, at which point it wraps down to a lower address and increments from there back to the start address
- for AxBURST=FIXED the address for each transfer in the transaction does not change
- note that AxADDR can indicate an unaligned start address (not aligned to AxSIZE) for INCR and FIXED burst types. When incrementing this address for INCR bursts, all subsequent transfers are to aligned addresses. So if you signal an INCR burst with AxSIZE=0x2 (32-bit) and a start address of 0x1 (not 32-bit aligned), the 2nd transfer in the burst will be to 0x4 (the first 32-bit aligned address after 0x1).
In your waveform it looks like your master is signalling lots of 16-transfer (AWLEN=0xf) 32-bit wide (AWSIZE=0x2) transactions, all starting at AWADDR=0x0. Each time AWVALID and AWREADY are both sampled high on ACLK rising indicates another transaction starting
1) AWSIZE and AWLEN together indicate the maximum number of bytes that this transaction can write (4x16=64 bytes), but each data transfer comes with a WSTRB signal indicating which of the bytes within the AWSIZE indicated transfer width actually contain valid data, so WSTRB needs to be checked for each data transfer to see the actual amount of data that is transferred.
2) AWADDR=0x0 indicates the start address, AWSIZE indicates address increments of 0x4, and AWLEN indicates 16 transfers, so the addresses being accessed are 0x0, 0x4, 0x8, 0xC, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24, 0x28, 0x2C, 0x30, 0x34, 0x38 and 0x3C.
3) Table A4-5 in the AXI specification describes AxCACHE=0x3 as indicating transactions to memory type "Normal non-cacheable, bufferable", and the requirements for this memory type are then explained in the sections of the protocol after this table.
Hopefully that answers all of your questions.